Robert E. Fennema

Array ( [id] => 8266567 [patent_doc_number] => 20120165993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'Self-Programming Thermostat System, Method and Computer Program Product' [patent_app_type] => utility [patent_app_number] => 13/284448 [patent_app_country] => US [patent_app_date] => 2011-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12514 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13284448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8721891 [patent_doc_number] => 20130073108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'SYSTEM AND METHOD FOR REAL-TIME MONITORING OF POWER SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/238051 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3265 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13238051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9187062 [patent_doc_number] => 08627048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Mechanism for irrevocable transactions' [patent_app_type] => utility [patent_app_number] => 13/231575 [patent_app_country] => US [patent_app_date] => 2011-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7638 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13231575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7671614 [patent_doc_number] => 20110320883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'MEMORY-HAZARD DETECTION AND AVOIDANCE INSTRUCTIONS FOR VECTOR PROCESSING' [patent_app_type] => utility [patent_app_number] => 13/224170 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7153 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13224170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7671521 [patent_doc_number] => 20110320790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'Link Stack Repair of Erroneous Speculative Update' [patent_app_type] => utility [patent_app_number] => 13/212654 [patent_app_country] => US [patent_app_date] => 2011-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6554 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13212654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7779624 [patent_doc_number] => 20120041583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'MEASUREMENT SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/210784 [patent_app_country] => US [patent_app_date] => 2011-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5249 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20120041583.pdf [firstpage_image] =>[orig_patent_app_number] => 13210784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6093995 [patent_doc_number] => 20110219220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'Link Stack Repair of Erroneous Speculative Update' [patent_app_type] => utility [patent_app_number] => 13/108227 [patent_app_country] => US [patent_app_date] => 2011-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4979 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20110219220.pdf [firstpage_image] =>[orig_patent_app_number] => 13108227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9035519 [patent_doc_number] => 20130238157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'ENERGY MANAGEMENT SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/642216 [patent_app_country] => US [patent_app_date] => 2011-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6808 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13642216 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8552225 [patent_doc_number] => 08327123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'Maximized memory throughput on parallel processing devices' [patent_app_type] => utility [patent_app_number] => 13/069384 [patent_app_country] => US [patent_app_date] => 2011-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13069384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9358553 [patent_doc_number] => 08677107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Apparatus and method for handling exception events' [patent_app_type] => utility [patent_app_number] => 13/064108 [patent_app_country] => US [patent_app_date] => 2011-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10273 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13064108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6020321 [patent_doc_number] => 20110225400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'Device for Testing a Multitasking Computation Architecture and Corresponding Test Method' [patent_app_type] => utility [patent_app_number] => 13/036919 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2716 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20110225400.pdf [firstpage_image] =>[orig_patent_app_number] => 13036919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9348088 [patent_doc_number] => 08667251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Electronic chip and integrated circuit including a split routing unit having first-level routers for intra-layer transmissions and second-level routers for inter-layer transmissions and transmissions to the processing units' [patent_app_type] => utility [patent_app_number] => 13/027613 [patent_app_country] => US [patent_app_date] => 2011-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4720 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13027613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8045937 [patent_doc_number] => 20120072704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => '\"OR\" BIT MATRIX MULTIPLY VECTOR INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 13/020358 [patent_app_country] => US [patent_app_date] => 2011-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2112 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20120072704.pdf [firstpage_image] =>[orig_patent_app_number] => 13020358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6164782 [patent_doc_number] => 20110160914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'TILT SENSOR APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/963294 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20110160914.pdf [firstpage_image] =>[orig_patent_app_number] => 12963294 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8574721 [patent_doc_number] => 08341382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Memory accelerator buffer replacement method and system' [patent_app_type] => utility [patent_app_number] => 12/895406 [patent_app_country] => US [patent_app_date] => 2010-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4200 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12895406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8333382 [patent_doc_number] => 20120200087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'Management System for Operating a Wind Energy Plant and Method Using the Management System' [patent_app_type] => utility [patent_app_number] => 13/392877 [patent_app_country] => US [patent_app_date] => 2010-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3207 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13392877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6533384 [patent_doc_number] => 20100262810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'CONCURRENT INSTRUCTION OPERATION METHOD AND DEVICE' [patent_app_type] => utility [patent_app_number] => 12/820874 [patent_app_country] => US [patent_app_date] => 2010-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4684 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20100262810.pdf [firstpage_image] =>[orig_patent_app_number] => 12820874 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6413633 [patent_doc_number] => 20100306513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'Processor Core and Method for Managing Program Counter Redirection in an Out-of-Order Processor Pipeline' [patent_app_type] => utility [patent_app_number] => 12/794370 [patent_app_country] => US [patent_app_date] => 2010-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7228 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20100306513.pdf [firstpage_image] =>[orig_patent_app_number] => 12794370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7582263 [patent_doc_number] => 20110296146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'HARDWARE INSTRUCTIONS TO ACCELERATE TABLE-DRIVEN MATHEMATICAL FUNCTION EVALUATION' [patent_app_type] => utility [patent_app_number] => 12/788570 [patent_app_country] => US [patent_app_date] => 2010-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20110296146.pdf [firstpage_image] =>[orig_patent_app_number] => 12788570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7582266 [patent_doc_number] => 20110296149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'Instruction Set Architecture Extensions for Performing Power Versus Performance Tradeoffs' [patent_app_type] => utility [patent_app_number] => 12/788940 [patent_app_country] => US [patent_app_date] => 2010-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20110296149.pdf [firstpage_image] =>[orig_patent_app_number] => 12788940 [rel_patent_id] =>[rel_patent_doc_number] =>)