Search

Robert E. Mates

Examiner (ID: 15294, Phone: (571)270-5293 , Office: P/2834 )

Most Active Art Unit
2834
Art Unit(s)
2832, 2834
Total Applications
528
Issued Applications
266
Pending Applications
81
Abandoned Applications
200

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11532570 [patent_doc_number] => 20170092547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'Methods of Fabricating Semiconductor Devices Including Complementary Metal Oxide Semiconductor Transistors' [patent_app_type] => utility [patent_app_number] => 15/234170 [patent_app_country] => US [patent_app_date] => 2016-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6236 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15234170 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/234170
Methods of fabricating semiconductor devices including complementary metal oxide semiconductor transistors Aug 10, 2016 Issued
Array ( [id] => 11446437 [patent_doc_number] => 20170047458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'HYDROGENATION OF PASSIVATED CONTACTS' [patent_app_type] => utility [patent_app_number] => 15/234586 [patent_app_country] => US [patent_app_date] => 2016-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5869 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15234586 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/234586
Hydrogenation of passivated contacts Aug 10, 2016 Issued
Array ( [id] => 13214767 [patent_doc_number] => 10121759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => On-bonder automatic overhang die optimization tool for wire bonding and related methods [patent_app_type] => utility [patent_app_number] => 15/234563 [patent_app_country] => US [patent_app_date] => 2016-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4686 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15234563 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/234563
On-bonder automatic overhang die optimization tool for wire bonding and related methods Aug 10, 2016 Issued
Array ( [id] => 11459924 [patent_doc_number] => 20170053830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'WAFER PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 15/234587 [patent_app_country] => US [patent_app_date] => 2016-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5615 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15234587 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/234587
Wafer processing method using adhesive tape to pick up device chips Aug 10, 2016 Issued
Array ( [id] => 13098861 [patent_doc_number] => 10068775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Method of bonding supporting substrate with device substrate for fabricating semiconductor device [patent_app_type] => utility [patent_app_number] => 15/233918 [patent_app_country] => US [patent_app_date] => 2016-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3993 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15233918 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/233918
Method of bonding supporting substrate with device substrate for fabricating semiconductor device Aug 9, 2016 Issued
Array ( [id] => 13976623 [patent_doc_number] => 10217676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Method and apparatus for manufacturing a semiconductor device including a plurality of semiconductor chips connected with bumps [patent_app_type] => utility [patent_app_number] => 15/233914 [patent_app_country] => US [patent_app_date] => 2016-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4454 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15233914 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/233914
Method and apparatus for manufacturing a semiconductor device including a plurality of semiconductor chips connected with bumps Aug 9, 2016 Issued
Array ( [id] => 11623092 [patent_doc_number] => 20170133280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'METHOD FOR FABRICATING SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 15/233643 [patent_app_country] => US [patent_app_date] => 2016-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 10036 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15233643 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/233643
Method of inspecting device using first measurement and second measurement lights Aug 9, 2016 Issued
Array ( [id] => 12019744 [patent_doc_number] => 09812455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias' [patent_app_type] => utility [patent_app_number] => 15/218487 [patent_app_country] => US [patent_app_date] => 2016-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 4831 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15218487 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/218487
Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias Jul 24, 2016 Issued
Array ( [id] => 11132431 [patent_doc_number] => 20160329406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'REVERSE TONE SELF-ALIGNED CONTACT' [patent_app_type] => utility [patent_app_number] => 15/215845 [patent_app_country] => US [patent_app_date] => 2016-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15215845 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/215845
Reverse tone self-aligned contact Jul 20, 2016 Issued
Array ( [id] => 16448428 [patent_doc_number] => 10840359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Method of forming FinFET source/drain contact [patent_app_type] => utility [patent_app_number] => 16/087574 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 5815 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16087574 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/087574
Method of forming FinFET source/drain contact Jun 26, 2016 Issued
Array ( [id] => 11103967 [patent_doc_number] => 20160300937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'Semiconductor Device with Rear-Side Insert Structure' [patent_app_type] => utility [patent_app_number] => 15/188333 [patent_app_country] => US [patent_app_date] => 2016-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9249 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15188333 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/188333
Semiconductor device with rear-side insert structure Jun 20, 2016 Issued
Array ( [id] => 11353680 [patent_doc_number] => 20160372420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'Damascene Thin-Film Resistor with an Added Mask Layer' [patent_app_type] => utility [patent_app_number] => 15/184748 [patent_app_country] => US [patent_app_date] => 2016-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3256 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15184748 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/184748
Manufacturing a damascene thin-film resistor Jun 15, 2016 Issued
Array ( [id] => 12019653 [patent_doc_number] => 09812364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Method of fabricating semiconductor device with an overlay mask pattern' [patent_app_type] => utility [patent_app_number] => 15/184315 [patent_app_country] => US [patent_app_date] => 2016-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 55 [patent_no_of_words] => 9588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15184315 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/184315
Method of fabricating semiconductor device with an overlay mask pattern Jun 15, 2016 Issued
Array ( [id] => 11891121 [patent_doc_number] => 09761688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Method of fabricating semiconductor device with tilted preamorphized implant' [patent_app_type] => utility [patent_app_number] => 15/184347 [patent_app_country] => US [patent_app_date] => 2016-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 7604 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15184347 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/184347
Method of fabricating semiconductor device with tilted preamorphized implant Jun 15, 2016 Issued
Array ( [id] => 12012713 [patent_doc_number] => 09806034 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-31 [patent_title] => 'Semiconductor device with protected sidewalls and methods of manufacturing thereof' [patent_app_type] => utility [patent_app_number] => 15/183940 [patent_app_country] => US [patent_app_date] => 2016-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3290 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15183940 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/183940
Semiconductor device with protected sidewalls and methods of manufacturing thereof Jun 15, 2016 Issued
Array ( [id] => 12195827 [patent_doc_number] => 09899565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Method of manufacturing semiconductor substrate including separating two semiconductor layers from a growth substrate' [patent_app_type] => utility [patent_app_number] => 15/183869 [patent_app_country] => US [patent_app_date] => 2016-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 14838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15183869 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/183869
Method of manufacturing semiconductor substrate including separating two semiconductor layers from a growth substrate Jun 15, 2016 Issued
Array ( [id] => 11353668 [patent_doc_number] => 20160372408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'METHODS OF MANUFACTURING PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/183868 [patent_app_country] => US [patent_app_date] => 2016-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15183868 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/183868
Methods of manufacturing printed circuit board and semiconductor package Jun 15, 2016 Issued
Array ( [id] => 11353583 [patent_doc_number] => 20160372324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'Deposition Methods For Uniform And Conformal Hybrid Titanium Oxide Films' [patent_app_type] => utility [patent_app_number] => 15/184521 [patent_app_country] => US [patent_app_date] => 2016-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15184521 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/184521
Deposition methods for uniform and conformal hybrid titanium oxide films Jun 15, 2016 Issued
Array ( [id] => 11385867 [patent_doc_number] => 20170011922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'APPARATUS AND METHOD FOR LIGHT-IRRADIATION HEAT TREATMENT' [patent_app_type] => utility [patent_app_number] => 15/183893 [patent_app_country] => US [patent_app_date] => 2016-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8461 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15183893 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/183893
Apparatus and method for light-irradiation heat treatment Jun 15, 2016 Issued
Array ( [id] => 13709057 [patent_doc_number] => 20170365483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => ATOMIC LAYER DEPOSITION METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/183118 [patent_app_country] => US [patent_app_date] => 2016-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15183118 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/183118
Atomic layer deposition method for manufacturing semiconductor structure Jun 14, 2016 Issued
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