
Robert E. Tallman
Examiner (ID: 6476, Phone: (571)270-3958 , Office: P/2872 )
| Most Active Art Unit | 2872 |
| Art Unit(s) | 2872 |
| Total Applications | 927 |
| Issued Applications | 717 |
| Pending Applications | 91 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4797538
[patent_doc_number] => 20080009124
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-10
[patent_title] => 'Method of forming a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/824626
[patent_app_country] => US
[patent_app_date] => 2007-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6986
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0009/20080009124.pdf
[firstpage_image] =>[orig_patent_app_number] => 11824626
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/824626 | Method of forming a semiconductor device | Jul 1, 2007 | Abandoned |
Array
(
[id] => 4657709
[patent_doc_number] => 20080026570
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-31
[patent_title] => 'METHOD OF FORMING A METAL LINE OF A SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/771486
[patent_app_country] => US
[patent_app_date] => 2007-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1487
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0026/20080026570.pdf
[firstpage_image] =>[orig_patent_app_number] => 11771486
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/771486 | Method of forming a metal line of a semiconductor memory device | Jun 28, 2007 | Issued |
Array
(
[id] => 4688270
[patent_doc_number] => 20080032451
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-07
[patent_title] => 'METHOD OF PROVIDING INVERTED PYRAMID MULTI-DIE PACKAGE REDUCING WIRE SWEEP AND WEAKENING TORQUES'
[patent_app_type] => utility
[patent_app_number] => 11/767535
[patent_app_country] => US
[patent_app_date] => 2007-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3256
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0032/20080032451.pdf
[firstpage_image] =>[orig_patent_app_number] => 11767535
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/767535 | METHOD OF PROVIDING INVERTED PYRAMID MULTI-DIE PACKAGE REDUCING WIRE SWEEP AND WEAKENING TORQUES | Jun 24, 2007 | Abandoned |
Array
(
[id] => 5199284
[patent_doc_number] => 20070298602
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-27
[patent_title] => 'Method for Applying Solder to Redistribution Lines'
[patent_app_type] => utility
[patent_app_number] => 11/766326
[patent_app_country] => US
[patent_app_date] => 2007-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2863
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0298/20070298602.pdf
[firstpage_image] =>[orig_patent_app_number] => 11766326
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/766326 | Method for applying solder to redistribution lines | Jun 20, 2007 | Issued |
Array
(
[id] => 4608961
[patent_doc_number] => 07994048
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-09
[patent_title] => 'Method of manufacturing a through electrode'
[patent_app_type] => utility
[patent_app_number] => 11/765696
[patent_app_country] => US
[patent_app_date] => 2007-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 22
[patent_no_of_words] => 6942
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/994/07994048.pdf
[firstpage_image] =>[orig_patent_app_number] => 11765696
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/765696 | Method of manufacturing a through electrode | Jun 19, 2007 | Issued |
Array
(
[id] => 4852638
[patent_doc_number] => 20080318381
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-25
[patent_title] => 'METHODS OF FORMING HIGH DENSITY SEMICONDUCTOR DEVICES USING RECURSIVE SPACER TECHNIQUE'
[patent_app_type] => utility
[patent_app_number] => 11/765866
[patent_app_country] => US
[patent_app_date] => 2007-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 10348
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0318/20080318381.pdf
[firstpage_image] =>[orig_patent_app_number] => 11765866
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/765866 | Methods of forming high density semiconductor devices using recursive spacer technique | Jun 19, 2007 | Issued |
Array
(
[id] => 4803155
[patent_doc_number] => 20080014743
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-17
[patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR INTERCONNECTIONS'
[patent_app_type] => utility
[patent_app_number] => 11/765006
[patent_app_country] => US
[patent_app_date] => 2007-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7145
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0014/20080014743.pdf
[firstpage_image] =>[orig_patent_app_number] => 11765006
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/765006 | Method of fabricating semiconductor interconnections | Jun 18, 2007 | Issued |
Array
(
[id] => 9496417
[patent_doc_number] => 08735230
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-27
[patent_title] => 'Method for manufacturing a semiconductor device including an impurity-doped silicon film'
[patent_app_type] => utility
[patent_app_number] => 11/765116
[patent_app_country] => US
[patent_app_date] => 2007-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3808
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11765116
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/765116 | Method for manufacturing a semiconductor device including an impurity-doped silicon film | Jun 18, 2007 | Issued |
Array
(
[id] => 4551907
[patent_doc_number] => 07820544
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-26
[patent_title] => 'Method for forming metal wiring of semiconductor device and a semiconductor device manufactured by the same'
[patent_app_type] => utility
[patent_app_number] => 11/764315
[patent_app_country] => US
[patent_app_date] => 2007-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 1769
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/820/07820544.pdf
[firstpage_image] =>[orig_patent_app_number] => 11764315
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/764315 | Method for forming metal wiring of semiconductor device and a semiconductor device manufactured by the same | Jun 17, 2007 | Issued |
Array
(
[id] => 4569191
[patent_doc_number] => 07858513
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-12-28
[patent_title] => 'Fabrication of self-aligned via holes in polymer thin films'
[patent_app_type] => utility
[patent_app_number] => 11/764326
[patent_app_country] => US
[patent_app_date] => 2007-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 3656
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/858/07858513.pdf
[firstpage_image] =>[orig_patent_app_number] => 11764326
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/764326 | Fabrication of self-aligned via holes in polymer thin films | Jun 17, 2007 | Issued |
Array
(
[id] => 7965723
[patent_doc_number] => 07939378
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-10
[patent_title] => 'Palladium-spot leadframes for high adhesion semiconductor devices and method of fabrication'
[patent_app_type] => utility
[patent_app_number] => 11/763565
[patent_app_country] => US
[patent_app_date] => 2007-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 4543
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 22
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/939/07939378.pdf
[firstpage_image] =>[orig_patent_app_number] => 11763565
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/763565 | Palladium-spot leadframes for high adhesion semiconductor devices and method of fabrication | Jun 14, 2007 | Issued |
Array
(
[id] => 5136
[patent_doc_number] => 07816754
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-19
[patent_title] => 'Ball grid array package construction with raised solder ball pads'
[patent_app_type] => utility
[patent_app_number] => 11/762479
[patent_app_country] => US
[patent_app_date] => 2007-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4446
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/816/07816754.pdf
[firstpage_image] =>[orig_patent_app_number] => 11762479
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/762479 | Ball grid array package construction with raised solder ball pads | Jun 12, 2007 | Issued |
Array
(
[id] => 7692010
[patent_doc_number] => 20070232023
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'ROOM TEMPERATURE METAL DIRECT BONDING'
[patent_app_type] => utility
[patent_app_number] => 11/758386
[patent_app_country] => US
[patent_app_date] => 2007-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 9088
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0232/20070232023.pdf
[firstpage_image] =>[orig_patent_app_number] => 11758386
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/758386 | Room temperature metal direct bonding | Jun 4, 2007 | Issued |
Array
(
[id] => 5088833
[patent_doc_number] => 20070228472
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'SILICON DEVICE ON SI: C-OI AND SGOI AND METHOD OF MANUFACTURE'
[patent_app_type] => utility
[patent_app_number] => 11/757874
[patent_app_country] => US
[patent_app_date] => 2007-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4596
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0228/20070228472.pdf
[firstpage_image] =>[orig_patent_app_number] => 11757874
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/757874 | Silicon device on Si:C-OI and SGOI and method of manufacture | Jun 3, 2007 | Issued |
Array
(
[id] => 7692054
[patent_doc_number] => 20070231979
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'SILICON DEVICE ON SI: C-OI AND SGOI AND METHOD OF MANUFACTURE'
[patent_app_type] => utility
[patent_app_number] => 11/757883
[patent_app_country] => US
[patent_app_date] => 2007-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4596
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0231/20070231979.pdf
[firstpage_image] =>[orig_patent_app_number] => 11757883
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/757883 | Silicon device on Si:C SOI and SiGe and method of manufacture | Jun 3, 2007 | Issued |
Array
(
[id] => 5259177
[patent_doc_number] => 20070212809
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-13
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING SILICON-DIFFUSED METAL WIRING LAYER AND ITS MANUFACTURING METHOD'
[patent_app_type] => utility
[patent_app_number] => 11/750116
[patent_app_country] => US
[patent_app_date] => 2007-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 88
[patent_figures_cnt] => 88
[patent_no_of_words] => 14873
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20070212809.pdf
[firstpage_image] =>[orig_patent_app_number] => 11750116
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/750116 | Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method | May 16, 2007 | Issued |
Array
(
[id] => 5063172
[patent_doc_number] => 20070224812
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-27
[patent_title] => 'Pattern film forming method and pattern film forming apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/798708
[patent_app_country] => US
[patent_app_date] => 2007-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 12493
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0224/20070224812.pdf
[firstpage_image] =>[orig_patent_app_number] => 11798708
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/798708 | Pattern film forming method and pattern film forming apparatus | May 15, 2007 | Issued |
Array
(
[id] => 14710
[patent_doc_number] => 07804178
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-28
[patent_title] => 'Semiconductor component with surface mountable devices and method for producing the same'
[patent_app_type] => utility
[patent_app_number] => 11/748135
[patent_app_country] => US
[patent_app_date] => 2007-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1981
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/804/07804178.pdf
[firstpage_image] =>[orig_patent_app_number] => 11748135
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/748135 | Semiconductor component with surface mountable devices and method for producing the same | May 13, 2007 | Issued |
Array
(
[id] => 4599377
[patent_doc_number] => 07977155
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-12
[patent_title] => 'Wafer-level flip-chip assembly methods'
[patent_app_type] => utility
[patent_app_number] => 11/800386
[patent_app_country] => US
[patent_app_date] => 2007-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 2646
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/977/07977155.pdf
[firstpage_image] =>[orig_patent_app_number] => 11800386
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/800386 | Wafer-level flip-chip assembly methods | May 3, 2007 | Issued |
Array
(
[id] => 7530331
[patent_doc_number] => 07842553
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-30
[patent_title] => 'Cooling micro-channels'
[patent_app_type] => utility
[patent_app_number] => 11/796235
[patent_app_country] => US
[patent_app_date] => 2007-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 2580
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/842/07842553.pdf
[firstpage_image] =>[orig_patent_app_number] => 11796235
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/796235 | Cooling micro-channels | Apr 26, 2007 | Issued |