Robert Edward Fuller

Array ( [id] => 1248911 [patent_doc_number] => 06678830 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Method and apparatus for an ACPI compliant keyboard sleep key' [patent_app_type] => B1 [patent_app_number] => 09/347065 [patent_app_country] => US [patent_app_date] => 1999-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4891 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678830.pdf [firstpage_image] =>[orig_patent_app_number] => 09347065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1418567 [patent_doc_number] => 06546449 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Video controller for accessing data in a system and method thereof' [patent_app_type] => B1 [patent_app_number] => 09/347201 [patent_app_country] => US [patent_app_date] => 1999-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5613 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546449.pdf [firstpage_image] =>[orig_patent_app_number] => 09347201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1524841 [patent_doc_number] => 06415347 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Hardware attention management circuit and method for parallel SCSI host adapters' [patent_app_type] => B1 [patent_app_number] => 09/344291 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415347.pdf [firstpage_image] =>[orig_patent_app_number] => 09344291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6793454 [patent_doc_number] => 20030088798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'SYSTEM HAVING DEVICES CONNECTED VIA COMMUNICATION LINES' [patent_app_type] => new [patent_app_number] => 09/344509 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14419 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20030088798.pdf [firstpage_image] =>[orig_patent_app_number] => 09344509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1459945 [patent_doc_number] => 06463488 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Apparatus and method for testing master logic units within a data processing apparatus' [patent_app_type] => B1 [patent_app_number] => 09/332526 [patent_app_country] => US [patent_app_date] => 1999-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5635 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463488.pdf [firstpage_image] =>[orig_patent_app_number] => 09332526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1519637 [patent_doc_number] => 06421755 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'System resource assignment for a hot inserted device' [patent_app_type] => B1 [patent_app_number] => 09/320263 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6252 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421755.pdf [firstpage_image] =>[orig_patent_app_number] => 09320263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1475092 [patent_doc_number] => 06408397 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Using RTC wake-up to enable recovery from power failures' [patent_app_type] => B1 [patent_app_number] => 09/317309 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2886 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408397.pdf [firstpage_image] =>[orig_patent_app_number] => 09317309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 524325 [patent_doc_number] => 07197589 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-27 [patent_title] => 'System and method for providing access to a bus' [patent_app_type] => utility [patent_app_number] => 09/315806 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1700 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/197/07197589.pdf [firstpage_image] =>[orig_patent_app_number] => 09315806 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1509073 [patent_doc_number] => 06467041 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Third party host packet replication' [patent_app_type] => B1 [patent_app_number] => 09/306187 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3445 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467041.pdf [firstpage_image] =>[orig_patent_app_number] => 09306187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4373523 [patent_doc_number] => 06202117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Host adapter integrated circuit having autoaccess pause' [patent_app_type] => 1 [patent_app_number] => 9/302017 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 6 [patent_no_of_words] => 6562 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202117.pdf [firstpage_image] =>[orig_patent_app_number] => 302017 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7001737 [patent_doc_number] => 20010054123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'IEEE 1394 ACTIVE WALL DISCONNECT AND AIRCRAFT QUALIFIED CABLE' [patent_app_type] => new [patent_app_number] => 09/300035 [patent_app_country] => US [patent_app_date] => 1999-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7760 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20010054123.pdf [firstpage_image] =>[orig_patent_app_number] => 09300035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1521817 [patent_doc_number] => 06502203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method and apparatus for cluster system operation' [patent_app_type] => B2 [patent_app_number] => 09/293587 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4563 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502203.pdf [firstpage_image] =>[orig_patent_app_number] => 09293587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1580259 [patent_doc_number] => 06470408 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Apparatus and method for delivering interrupts via an APIC bus to IA-32 processors' [patent_app_type] => B1 [patent_app_number] => 09/292131 [patent_app_country] => US [patent_app_date] => 1999-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470408.pdf [firstpage_image] =>[orig_patent_app_number] => 09292131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4407970 [patent_doc_number] => 06298066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Single wire bus interface for multidrop applications' [patent_app_type] => 1 [patent_app_number] => 9/292073 [patent_app_country] => US [patent_app_date] => 1999-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4422 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298066.pdf [firstpage_image] =>[orig_patent_app_number] => 292073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6698129 [patent_doc_number] => 20030110323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'INFORMATION PROCESSING APPARATUS, POWER CONTROL METHOD AND RECORDING MEDIUM TO CONTROL A PLURALITY OF DRIVING UNITS ACCORDING TO THE TYPE OF DATA TO BE PROCESSED' [patent_app_type] => new [patent_app_number] => 09/285879 [patent_app_country] => US [patent_app_date] => 1999-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6925 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20030110323.pdf [firstpage_image] =>[orig_patent_app_number] => 09285879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 580824 [patent_doc_number] => 07472215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-30 [patent_title] => 'Portable computer system with thermal enhancements and multiple power modes of operation' [patent_app_type] => utility [patent_app_number] => 09/282141 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4327 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 459 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/472/07472215.pdf [firstpage_image] =>[orig_patent_app_number] => 09282141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1066645 [patent_doc_number] => 06851002 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Processing device with parallel mounting regions for component exchange' [patent_app_type] => utility [patent_app_number] => 09/647341 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3040 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/851/06851002.pdf [firstpage_image] =>[orig_patent_app_number] => 09647341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1557701 [patent_doc_number] => 06401219 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Failure analysis system, method for managing estimated logic status and information storage medium for programmed instruction of the method' [patent_app_type] => B1 [patent_app_number] => 09/275812 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12694 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401219.pdf [firstpage_image] =>[orig_patent_app_number] => 09275812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 390717 [patent_doc_number] => 07301313 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-27 [patent_title] => 'Multiple voltage regulators for use with a single load' [patent_app_type] => utility [patent_app_number] => 09/275273 [patent_app_country] => US [patent_app_date] => 1999-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2884 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/301/07301313.pdf [firstpage_image] =>[orig_patent_app_number] => 09275273 [rel_patent_id] =>[rel_patent_doc_number] =>)