Search

Robert Edward Fuller

Examiner (ID: 19273, Phone: (571)272-6300 , Office: P/3676 )

Most Active Art Unit
3676
Art Unit(s)
3676, 3672
Total Applications
1121
Issued Applications
829
Pending Applications
108
Abandoned Applications
206

Applications

Application numberTitle of the applicationFiling DateStatus
09/248939 INTER-DEVICE SERIAL BUS PROTOCOL Jan 11, 1999 Abandoned
Array ( [id] => 4403796 [patent_doc_number] => 06263395 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'System and method for serial interrupt scanning' [patent_app_type] => 1 [patent_app_number] => 9/227510 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6785 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263395.pdf [firstpage_image] =>[orig_patent_app_number] => 227510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/227510
System and method for serial interrupt scanning Jan 5, 1999 Issued
Array ( [id] => 7630008 [patent_doc_number] => 06636931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'System and method for switching signals over twisted-pair wires' [patent_app_type] => B2 [patent_app_number] => 09/226869 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6436 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636931.pdf [firstpage_image] =>[orig_patent_app_number] => 09226869 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/226869
System and method for switching signals over twisted-pair wires Jan 5, 1999 Issued
Array ( [id] => 4176531 [patent_doc_number] => 06157978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Multimedia round-robin arbitration with phantom slots for super-priority real-time agent' [patent_app_type] => 1 [patent_app_number] => 9/226398 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8274 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157978.pdf [firstpage_image] =>[orig_patent_app_number] => 226398 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/226398
Multimedia round-robin arbitration with phantom slots for super-priority real-time agent Jan 5, 1999 Issued
Array ( [id] => 7644147 [patent_doc_number] => 06473827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-29 [patent_title] => 'Distributed multi-fabric interconnect' [patent_app_type] => B2 [patent_app_number] => 09/218954 [patent_app_country] => US [patent_app_date] => 1998-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8378 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473827.pdf [firstpage_image] =>[orig_patent_app_number] => 09218954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/218954
Distributed multi-fabric interconnect Dec 21, 1998 Issued
09/217110 UNIVERSAL DOCKING STATION Dec 20, 1998 Abandoned
Array ( [id] => 4381091 [patent_doc_number] => 06256699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Reliable interrupt reception over buffered bus' [patent_app_type] => 1 [patent_app_number] => 9/212016 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2983 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256699.pdf [firstpage_image] =>[orig_patent_app_number] => 212016 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/212016
Reliable interrupt reception over buffered bus Dec 14, 1998 Issued
Array ( [id] => 1466460 [patent_doc_number] => 06393582 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Error self-checking and recovery using lock-step processor pair architecture' [patent_app_type] => B1 [patent_app_number] => 09/209635 [patent_app_country] => US [patent_app_date] => 1998-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5859 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393582.pdf [firstpage_image] =>[orig_patent_app_number] => 09209635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/209635
Error self-checking and recovery using lock-step processor pair architecture Dec 9, 1998 Issued
Array ( [id] => 4424042 [patent_doc_number] => 06301630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Interrupt response in a multiple set buffer pool bus bridge' [patent_app_type] => 1 [patent_app_number] => 9/210127 [patent_app_country] => US [patent_app_date] => 1998-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 9312 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301630.pdf [firstpage_image] =>[orig_patent_app_number] => 210127 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/210127
Interrupt response in a multiple set buffer pool bus bridge Dec 9, 1998 Issued
09/205064 PROGRAMMABLE PULL-UP FOR A UNIVERSAL SERIAL BUS INTERFACE Dec 3, 1998 Abandoned
Array ( [id] => 1602130 [patent_doc_number] => 06385744 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Data recording medium, data recording method and data reproducing method' [patent_app_type] => B1 [patent_app_number] => 09/204157 [patent_app_country] => US [patent_app_date] => 1998-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 12102 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385744.pdf [firstpage_image] =>[orig_patent_app_number] => 09204157 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/204157
Data recording medium, data recording method and data reproducing method Dec 2, 1998 Issued
Array ( [id] => 1585038 [patent_doc_number] => 06449738 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Apparatus for bus frequency independent wrap I/O testing and method therefor' [patent_app_type] => B1 [patent_app_number] => 09/204923 [patent_app_country] => US [patent_app_date] => 1998-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2656 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449738.pdf [firstpage_image] =>[orig_patent_app_number] => 09204923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/204923
Apparatus for bus frequency independent wrap I/O testing and method therefor Dec 2, 1998 Issued
Array ( [id] => 1519752 [patent_doc_number] => 06421792 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Data processing system and method for automatic recovery from an unsuccessful boot' [patent_app_type] => B1 [patent_app_number] => 09/204983 [patent_app_country] => US [patent_app_date] => 1998-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2349 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421792.pdf [firstpage_image] =>[orig_patent_app_number] => 09204983 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/204983
Data processing system and method for automatic recovery from an unsuccessful boot Dec 2, 1998 Issued
Array ( [id] => 4373457 [patent_doc_number] => 06202112 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge' [patent_app_type] => 1 [patent_app_number] => 9/205351 [patent_app_country] => US [patent_app_date] => 1998-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3625 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202112.pdf [firstpage_image] =>[orig_patent_app_number] => 205351 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/205351
Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge Dec 2, 1998 Issued
Array ( [id] => 7642345 [patent_doc_number] => 06430701 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Data recording and reproducing method and apparatus using plurality of data recording and reproducing units, and computer-readable recording medium' [patent_app_type] => B1 [patent_app_number] => 09/204761 [patent_app_country] => US [patent_app_date] => 1998-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 15251 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430701.pdf [firstpage_image] =>[orig_patent_app_number] => 09204761 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/204761
Data recording and reproducing method and apparatus using plurality of data recording and reproducing units, and computer-readable recording medium Dec 1, 1998 Issued
Array ( [id] => 4422943 [patent_doc_number] => 06272645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method and control circuit for waking up a computer system from standby mode' [patent_app_type] => 1 [patent_app_number] => 9/191799 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3119 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272645.pdf [firstpage_image] =>[orig_patent_app_number] => 191799 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191799
Method and control circuit for waking up a computer system from standby mode Nov 12, 1998 Issued
Array ( [id] => 4391411 [patent_doc_number] => 06289406 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Optimizing the performance of asynchronous bus bridges with dynamic transactions' [patent_app_type] => 1 [patent_app_number] => 9/187325 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6347 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289406.pdf [firstpage_image] =>[orig_patent_app_number] => 187325 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187325
Optimizing the performance of asynchronous bus bridges with dynamic transactions Nov 5, 1998 Issued
Array ( [id] => 4206219 [patent_doc_number] => 06131114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'System for interchanging data between data processor units having processors interconnected by a common bus' [patent_app_type] => 1 [patent_app_number] => 9/187086 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 22 [patent_no_of_words] => 5737 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/131/06131114.pdf [firstpage_image] =>[orig_patent_app_number] => 187086 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187086
System for interchanging data between data processor units having processors interconnected by a common bus Nov 4, 1998 Issued
Array ( [id] => 1011310 [patent_doc_number] => 06901457 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-31 [patent_title] => 'Multiple mode communications system' [patent_app_type] => utility [patent_app_number] => 09/186064 [patent_app_country] => US [patent_app_date] => 1998-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6789 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/901/06901457.pdf [firstpage_image] =>[orig_patent_app_number] => 09186064 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186064
Multiple mode communications system Nov 3, 1998 Issued
Array ( [id] => 6908548 [patent_doc_number] => 20010011315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-02 [patent_title] => 'METHOD AND APPARATUS FOR PROVIDING INTELLIGENT POWER MANAGEMENT' [patent_app_type] => new [patent_app_number] => 09/185674 [patent_app_country] => US [patent_app_date] => 1998-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3891 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20010011315.pdf [firstpage_image] =>[orig_patent_app_number] => 09185674 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/185674
Method and apparatus for providing intelligent power management Nov 3, 1998 Issued
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