
Robert Edward Fuller
Examiner (ID: 19273, Phone: (571)272-6300 , Office: P/3676 )
| Most Active Art Unit | 3676 |
| Art Unit(s) | 3676, 3672 |
| Total Applications | 1121 |
| Issued Applications | 829 |
| Pending Applications | 108 |
| Abandoned Applications | 206 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4291980
[patent_doc_number] => 06247082
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-12
[patent_title] => 'Method and circuit for providing handshaking to transact information across multiple clock domains'
[patent_app_type] => 1
[patent_app_number] => 9/186209
[patent_app_country] => US
[patent_app_date] => 1998-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4775
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/247/06247082.pdf
[firstpage_image] =>[orig_patent_app_number] => 186209
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/186209 | Method and circuit for providing handshaking to transact information across multiple clock domains | Nov 2, 1998 | Issued |
Array
(
[id] => 1524963
[patent_doc_number] => 06415388
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-02
[patent_title] => 'Method and apparatus for power throttling in a microprocessor using a closed loop feedback system'
[patent_app_type] => B1
[patent_app_number] => 09/183255
[patent_app_country] => US
[patent_app_date] => 1998-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3802
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/415/06415388.pdf
[firstpage_image] =>[orig_patent_app_number] => 09183255
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/183255 | Method and apparatus for power throttling in a microprocessor using a closed loop feedback system | Oct 29, 1998 | Issued |
Array
(
[id] => 4402755
[patent_doc_number] => 06279117
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-21
[patent_title] => 'Recovery support method for recovering from failure of an external storage device'
[patent_app_type] => 1
[patent_app_number] => 9/182439
[patent_app_country] => US
[patent_app_date] => 1998-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 24
[patent_no_of_words] => 12266
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 511
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/279/06279117.pdf
[firstpage_image] =>[orig_patent_app_number] => 182439
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/182439 | Recovery support method for recovering from failure of an external storage device | Oct 29, 1998 | Issued |
Array
(
[id] => 1524963
[patent_doc_number] => 06415388
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-02
[patent_title] => 'Method and apparatus for power throttling in a microprocessor using a closed loop feedback system'
[patent_app_type] => B1
[patent_app_number] => 09/183255
[patent_app_country] => US
[patent_app_date] => 1998-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3802
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/415/06415388.pdf
[firstpage_image] =>[orig_patent_app_number] => 09183255
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/183255 | Method and apparatus for power throttling in a microprocessor using a closed loop feedback system | Oct 29, 1998 | Issued |
Array
(
[id] => 1524963
[patent_doc_number] => 06415388
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-02
[patent_title] => 'Method and apparatus for power throttling in a microprocessor using a closed loop feedback system'
[patent_app_type] => B1
[patent_app_number] => 09/183255
[patent_app_country] => US
[patent_app_date] => 1998-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3802
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/415/06415388.pdf
[firstpage_image] =>[orig_patent_app_number] => 09183255
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/183255 | Method and apparatus for power throttling in a microprocessor using a closed loop feedback system | Oct 29, 1998 | Issued |
Array
(
[id] => 1524963
[patent_doc_number] => 06415388
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-02
[patent_title] => 'Method and apparatus for power throttling in a microprocessor using a closed loop feedback system'
[patent_app_type] => B1
[patent_app_number] => 09/183255
[patent_app_country] => US
[patent_app_date] => 1998-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3802
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/415/06415388.pdf
[firstpage_image] =>[orig_patent_app_number] => 09183255
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/183255 | Method and apparatus for power throttling in a microprocessor using a closed loop feedback system | Oct 29, 1998 | Issued |
Array
(
[id] => 1567681
[patent_doc_number] => 06438716
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-20
[patent_title] => 'Composition of error messages in an error message system based upon non-local contextual information'
[patent_app_type] => B1
[patent_app_number] => 09/177032
[patent_app_country] => US
[patent_app_date] => 1998-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 5398
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/438/06438716.pdf
[firstpage_image] =>[orig_patent_app_number] => 09177032
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/177032 | Composition of error messages in an error message system based upon non-local contextual information | Oct 21, 1998 | Issued |
Array
(
[id] => 7118685
[patent_doc_number] => 20010001878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-05-24
[patent_title] => 'SYSTEM AND METHOD FOR PROCESSOR DUAL VOLTAGE DETECTION AND OVER STRESS PROTECTION'
[patent_app_type] => new-utility
[patent_app_number] => 09/176737
[patent_app_country] => US
[patent_app_date] => 1998-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5921
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20010001878.pdf
[firstpage_image] =>[orig_patent_app_number] => 09176737
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/176737 | System and method for processor dual voltage detection and over stress protection | Oct 20, 1998 | Issued |
Array
(
[id] => 4151487
[patent_doc_number] => 06035358
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Upgrade CPU module with integral power supply'
[patent_app_type] => 1
[patent_app_number] => 9/170481
[patent_app_country] => US
[patent_app_date] => 1998-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2368
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/035/06035358.pdf
[firstpage_image] =>[orig_patent_app_number] => 170481
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/170481 | Upgrade CPU module with integral power supply | Oct 12, 1998 | Issued |
Array
(
[id] => 4424746
[patent_doc_number] => 06266787
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-24
[patent_title] => 'Method and apparatus for selecting stimulus locations during limited access circuit test'
[patent_app_type] => 1
[patent_app_number] => 9/169597
[patent_app_country] => US
[patent_app_date] => 1998-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 14208
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/266/06266787.pdf
[firstpage_image] =>[orig_patent_app_number] => 169597
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/169597 | Method and apparatus for selecting stimulus locations during limited access circuit test | Oct 8, 1998 | Issued |
Array
(
[id] => 4310791
[patent_doc_number] => 06212645
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-03
[patent_title] => 'Programmable and flexible power management unit'
[patent_app_type] => 1
[patent_app_number] => 9/169438
[patent_app_country] => US
[patent_app_date] => 1998-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 27
[patent_no_of_words] => 14970
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/212/06212645.pdf
[firstpage_image] =>[orig_patent_app_number] => 169438
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/169438 | Programmable and flexible power management unit | Oct 8, 1998 | Issued |
Array
(
[id] => 1539381
[patent_doc_number] => 06412084
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Control of computer peripherals'
[patent_app_type] => B1
[patent_app_number] => 09/155845
[patent_app_country] => US
[patent_app_date] => 1998-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2536
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/412/06412084.pdf
[firstpage_image] =>[orig_patent_app_number] => 09155845
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/155845 | Control of computer peripherals | Oct 6, 1998 | Issued |
Array
(
[id] => 4333730
[patent_doc_number] => 06317848
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-13
[patent_title] => 'System for tracking and automatically communicating printer failures and usage profile aspects'
[patent_app_type] => 1
[patent_app_number] => 9/160468
[patent_app_country] => US
[patent_app_date] => 1998-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2503
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/317/06317848.pdf
[firstpage_image] =>[orig_patent_app_number] => 160468
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/160468 | System for tracking and automatically communicating printer failures and usage profile aspects | Sep 23, 1998 | Issued |
Array
(
[id] => 4412777
[patent_doc_number] => 06298456
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Runtime detection of network loops'
[patent_app_type] => 1
[patent_app_number] => 9/160054
[patent_app_country] => US
[patent_app_date] => 1998-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3524
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/298/06298456.pdf
[firstpage_image] =>[orig_patent_app_number] => 160054
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/160054 | Runtime detection of network loops | Sep 23, 1998 | Issued |
Array
(
[id] => 4335864
[patent_doc_number] => 06243835
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Test specification generation system and storage medium storing a test specification generation program'
[patent_app_type] => 1
[patent_app_number] => 9/154704
[patent_app_country] => US
[patent_app_date] => 1998-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 7770
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/243/06243835.pdf
[firstpage_image] =>[orig_patent_app_number] => 154704
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/154704 | Test specification generation system and storage medium storing a test specification generation program | Sep 16, 1998 | Issued |
Array
(
[id] => 4268897
[patent_doc_number] => 06138197
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'Apparatus and method for limit-based arbitration scheme'
[patent_app_type] => 1
[patent_app_number] => 9/154500
[patent_app_country] => US
[patent_app_date] => 1998-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3564
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/138/06138197.pdf
[firstpage_image] =>[orig_patent_app_number] => 154500
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/154500 | Apparatus and method for limit-based arbitration scheme | Sep 16, 1998 | Issued |
Array
(
[id] => 4403739
[patent_doc_number] => 06263390
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-17
[patent_title] => 'Two-port memory to connect a microprocessor bus to multiple peripherals'
[patent_app_type] => 1
[patent_app_number] => 9/136209
[patent_app_country] => US
[patent_app_date] => 1998-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 5329
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/263/06263390.pdf
[firstpage_image] =>[orig_patent_app_number] => 136209
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/136209 | Two-port memory to connect a microprocessor bus to multiple peripherals | Aug 17, 1998 | Issued |
Array
(
[id] => 4304531
[patent_doc_number] => 06269414
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-31
[patent_title] => 'Data rate doubler for electrical backplane'
[patent_app_type] => 1
[patent_app_number] => 9/115121
[patent_app_country] => US
[patent_app_date] => 1998-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3169
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/269/06269414.pdf
[firstpage_image] =>[orig_patent_app_number] => 115121
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/115121 | Data rate doubler for electrical backplane | Jul 13, 1998 | Issued |
Array
(
[id] => 4176954
[patent_doc_number] => 06105092
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-15
[patent_title] => 'Computer system including a device with a plurality of identifiers'
[patent_app_type] => 1
[patent_app_number] => 9/110653
[patent_app_country] => US
[patent_app_date] => 1998-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6551
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/105/06105092.pdf
[firstpage_image] =>[orig_patent_app_number] => 110653
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/110653 | Computer system including a device with a plurality of identifiers | Jul 6, 1998 | Issued |
Array
(
[id] => 4147183
[patent_doc_number] => 06128682
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-03
[patent_title] => 'Method and apparatus for bus isolation'
[patent_app_type] => 1
[patent_app_number] => 9/104837
[patent_app_country] => US
[patent_app_date] => 1998-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4904
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/128/06128682.pdf
[firstpage_image] =>[orig_patent_app_number] => 104837
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/104837 | Method and apparatus for bus isolation | Jun 24, 1998 | Issued |