Search

Robert Edward Fuller

Examiner (ID: 19273, Phone: (571)272-6300 , Office: P/3676 )

Most Active Art Unit
3676
Art Unit(s)
3676, 3672
Total Applications
1121
Issued Applications
829
Pending Applications
108
Abandoned Applications
206

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4088409 [patent_doc_number] => 06070208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Apparatus and method for implementing a versatile USB endpoint pipe' [patent_app_type] => 1 [patent_app_number] => 9/003963 [patent_app_country] => US [patent_app_date] => 1998-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 7197 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/070/06070208.pdf [firstpage_image] =>[orig_patent_app_number] => 003963 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/003963
Apparatus and method for implementing a versatile USB endpoint pipe Jan 6, 1998 Issued
Array ( [id] => 4211194 [patent_doc_number] => 06044430 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Real time interrupt handling for superscalar processors' [patent_app_type] => 1 [patent_app_number] => 8/992283 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5646 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044430.pdf [firstpage_image] =>[orig_patent_app_number] => 992283 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992283
Real time interrupt handling for superscalar processors Dec 16, 1997 Issued
09/314856 SYSTEM FOR INHIBITING THE OPERATION OF AN ELECTRONIC DEVICE DURING TAKE-OFF AND LANDING OF AN AIRCRAFT Nov 25, 1997 Abandoned
08/968084 ELECTRICAL PRECHARGE OF DEVICES BEING CONNECTED TO A DATA BUS Nov 11, 1997 Abandoned
Array ( [id] => 3994755 [patent_doc_number] => 05949772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Communication device' [patent_app_type] => 1 [patent_app_number] => 8/967904 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 49 [patent_no_of_words] => 21709 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949772.pdf [firstpage_image] =>[orig_patent_app_number] => 967904 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967904
Communication device Nov 11, 1997 Issued
Array ( [id] => 3993239 [patent_doc_number] => 05918061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Enhanced power managing unit (PMU) in a multiprocessor chip' [patent_app_type] => 1 [patent_app_number] => 8/966631 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2743 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918061.pdf [firstpage_image] =>[orig_patent_app_number] => 966631 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/966631
Enhanced power managing unit (PMU) in a multiprocessor chip Nov 9, 1997 Issued
Array ( [id] => 4057960 [patent_doc_number] => 05913067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Apparatus for adaptive power management of a computer system' [patent_app_type] => 1 [patent_app_number] => 8/961582 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4638 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913067.pdf [firstpage_image] =>[orig_patent_app_number] => 961582 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/961582
Apparatus for adaptive power management of a computer system Oct 30, 1997 Issued
Array ( [id] => 4257301 [patent_doc_number] => 06145038 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method and system for early slave forwarding of strictly ordered bus operations' [patent_app_type] => 1 [patent_app_number] => 8/833228 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3521 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145038.pdf [firstpage_image] =>[orig_patent_app_number] => 833228 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/833228
Method and system for early slave forwarding of strictly ordered bus operations Oct 30, 1997 Issued
Array ( [id] => 4099750 [patent_doc_number] => 06055597 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Bi-directional synchronizing buffer system' [patent_app_type] => 1 [patent_app_number] => 8/960777 [patent_app_country] => US [patent_app_date] => 1997-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9066 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055597.pdf [firstpage_image] =>[orig_patent_app_number] => 960777 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960777
Bi-directional synchronizing buffer system Oct 29, 1997 Issued
Array ( [id] => 4236260 [patent_doc_number] => 06041378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Integrated circuit device and method of communication therewith' [patent_app_type] => 1 [patent_app_number] => 8/960187 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 14773 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041378.pdf [firstpage_image] =>[orig_patent_app_number] => 960187 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960187
Integrated circuit device and method of communication therewith Oct 28, 1997 Issued
Array ( [id] => 4042585 [patent_doc_number] => 05903763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Method of recovering exclusive control instruction and multi-processor system using the same' [patent_app_type] => 1 [patent_app_number] => 8/955718 [patent_app_country] => US [patent_app_date] => 1997-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 8678 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903763.pdf [firstpage_image] =>[orig_patent_app_number] => 955718 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/955718
Method of recovering exclusive control instruction and multi-processor system using the same Oct 21, 1997 Issued
Array ( [id] => 4422288 [patent_doc_number] => 06173353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method and apparatus for dual bus memory transactions' [patent_app_type] => 1 [patent_app_number] => 8/954357 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3451 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173353.pdf [firstpage_image] =>[orig_patent_app_number] => 954357 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/954357
Method and apparatus for dual bus memory transactions Oct 19, 1997 Issued
Array ( [id] => 4194699 [patent_doc_number] => 06085273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Multi-processor computer system having memory space accessible to multiple processors' [patent_app_type] => 1 [patent_app_number] => 8/953790 [patent_app_country] => US [patent_app_date] => 1997-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3075 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085273.pdf [firstpage_image] =>[orig_patent_app_number] => 953790 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/953790
Multi-processor computer system having memory space accessible to multiple processors Oct 8, 1997 Issued
Array ( [id] => 4336844 [patent_doc_number] => 06249828 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method for the hot swap of a mass storage adapter on a system including a statically loaded adapter driver' [patent_app_type] => 1 [patent_app_number] => 8/942336 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 11476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249828.pdf [firstpage_image] =>[orig_patent_app_number] => 942336 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942336
Method for the hot swap of a mass storage adapter on a system including a statically loaded adapter driver Sep 30, 1997 Issued
Array ( [id] => 3837143 [patent_doc_number] => 05790875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Method for lowering power consumption in a computing device' [patent_app_type] => 1 [patent_app_number] => 8/939961 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3720 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790875.pdf [firstpage_image] =>[orig_patent_app_number] => 939961 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/939961
Method for lowering power consumption in a computing device Sep 28, 1997 Issued
Array ( [id] => 4160135 [patent_doc_number] => 06064646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Data communication apparatus and method' [patent_app_type] => 1 [patent_app_number] => 8/938679 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5133 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064646.pdf [firstpage_image] =>[orig_patent_app_number] => 938679 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938679
Data communication apparatus and method Sep 25, 1997 Issued
Array ( [id] => 4223627 [patent_doc_number] => 06078977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Hierarchical bus structure access system' [patent_app_type] => 1 [patent_app_number] => 8/922243 [patent_app_country] => US [patent_app_date] => 1997-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4138 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078977.pdf [firstpage_image] =>[orig_patent_app_number] => 922243 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/922243
Hierarchical bus structure access system Sep 1, 1997 Issued
Array ( [id] => 3989919 [patent_doc_number] => 05905906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Method and apparatus for configuring multiple printers on a network' [patent_app_type] => 1 [patent_app_number] => 8/906650 [patent_app_country] => US [patent_app_date] => 1997-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9101 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905906.pdf [firstpage_image] =>[orig_patent_app_number] => 906650 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/906650
Method and apparatus for configuring multiple printers on a network Aug 6, 1997 Issued
Array ( [id] => 3812180 [patent_doc_number] => 05781782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Electronic device with a power saving function' [patent_app_type] => 1 [patent_app_number] => 8/895103 [patent_app_country] => US [patent_app_date] => 1997-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3515 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781782.pdf [firstpage_image] =>[orig_patent_app_number] => 895103 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895103
Electronic device with a power saving function Jul 15, 1997 Issued
Array ( [id] => 1519690 [patent_doc_number] => 06421776 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Data processor having BIOS packing compression/decompression architecture' [patent_app_type] => B1 [patent_app_number] => 08/892822 [patent_app_country] => US [patent_app_date] => 1997-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4285 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421776.pdf [firstpage_image] =>[orig_patent_app_number] => 08892822 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892822
Data processor having BIOS packing compression/decompression architecture Jul 14, 1997 Issued
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