Search

Robert Edward Fuller

Examiner (ID: 19273, Phone: (571)272-6300 , Office: P/3676 )

Most Active Art Unit
3676
Art Unit(s)
3676, 3672
Total Applications
1121
Issued Applications
829
Pending Applications
108
Abandoned Applications
206

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4100825 [patent_doc_number] => 06018782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Flexible buffering scheme for inter-module on-chip communications' [patent_app_type] => 1 [patent_app_number] => 8/892415 [patent_app_country] => US [patent_app_date] => 1997-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4085 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018782.pdf [firstpage_image] =>[orig_patent_app_number] => 892415 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892415
Flexible buffering scheme for inter-module on-chip communications Jul 13, 1997 Issued
Array ( [id] => 3943461 [patent_doc_number] => 05878237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Apparatus, method and system for a comuter CPU and memory to PCI bridge having a pluarlity of physical PCI buses' [patent_app_type] => 1 [patent_app_number] => 8/893849 [patent_app_country] => US [patent_app_date] => 1997-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13964 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/878/05878237.pdf [firstpage_image] =>[orig_patent_app_number] => 893849 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/893849
Apparatus, method and system for a comuter CPU and memory to PCI bridge having a pluarlity of physical PCI buses Jul 10, 1997 Issued
Array ( [id] => 4374520 [patent_doc_number] => 06170031 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Read/write state machines for transferring data to/from host interface in a digital data storage system' [patent_app_type] => 1 [patent_app_number] => 8/889360 [patent_app_country] => US [patent_app_date] => 1997-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6314 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170031.pdf [firstpage_image] =>[orig_patent_app_number] => 889360 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/889360
Read/write state machines for transferring data to/from host interface in a digital data storage system Jul 7, 1997 Issued
Array ( [id] => 4118032 [patent_doc_number] => 06098137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Fault tolerant computer system' [patent_app_type] => 1 [patent_app_number] => 8/882504 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8553 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098137.pdf [firstpage_image] =>[orig_patent_app_number] => 882504 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882504
Fault tolerant computer system Jun 24, 1997 Issued
Array ( [id] => 3904817 [patent_doc_number] => 05778204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'High-speed dominant mode bus for differential signals' [patent_app_type] => 1 [patent_app_number] => 8/880252 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6765 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778204.pdf [firstpage_image] =>[orig_patent_app_number] => 880252 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/880252
High-speed dominant mode bus for differential signals Jun 22, 1997 Issued
Array ( [id] => 4199690 [patent_doc_number] => 06021452 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Computer system capable of symmetrical processing' [patent_app_type] => 1 [patent_app_number] => 8/879400 [patent_app_country] => US [patent_app_date] => 1997-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1954 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021452.pdf [firstpage_image] =>[orig_patent_app_number] => 879400 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879400
Computer system capable of symmetrical processing Jun 19, 1997 Issued
Array ( [id] => 4021765 [patent_doc_number] => 05987557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method and apparatus for implementing hardware protection domains in a system with no memory management unit (MMU)' [patent_app_type] => 1 [patent_app_number] => 8/879124 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8595 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987557.pdf [firstpage_image] =>[orig_patent_app_number] => 879124 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879124
Method and apparatus for implementing hardware protection domains in a system with no memory management unit (MMU) Jun 18, 1997 Issued
Array ( [id] => 4137955 [patent_doc_number] => 06073163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method and apparatus for enabling web-based execution of an application' [patent_app_type] => 1 [patent_app_number] => 8/872777 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6780 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073163.pdf [firstpage_image] =>[orig_patent_app_number] => 872777 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/872777
Method and apparatus for enabling web-based execution of an application Jun 9, 1997 Issued
Array ( [id] => 4002639 [patent_doc_number] => 05960180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Host adapter integrated circuit having autoaccess pause' [patent_app_type] => 1 [patent_app_number] => 8/869665 [patent_app_country] => US [patent_app_date] => 1997-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6469 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960180.pdf [firstpage_image] =>[orig_patent_app_number] => 869665 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/869665
Host adapter integrated circuit having autoaccess pause Jun 4, 1997 Issued
Array ( [id] => 4151473 [patent_doc_number] => 06035357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'IC card compatible with different supply voltages, IC card system comprising the same, and IC for the IC card' [patent_app_type] => 1 [patent_app_number] => 8/868154 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6250 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035357.pdf [firstpage_image] =>[orig_patent_app_number] => 868154 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/868154
IC card compatible with different supply voltages, IC card system comprising the same, and IC for the IC card Jun 2, 1997 Issued
Array ( [id] => 4057222 [patent_doc_number] => 05996037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'System and method for arbitrating multi-function access to a system bus' [patent_app_type] => 1 [patent_app_number] => 8/867992 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996037.pdf [firstpage_image] =>[orig_patent_app_number] => 867992 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/867992
System and method for arbitrating multi-function access to a system bus Jun 2, 1997 Issued
Array ( [id] => 3887564 [patent_doc_number] => 05838931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Method and apparatus for enabling a processor to access an external component through a private bus or a shared bus' [patent_app_type] => 1 [patent_app_number] => 8/854158 [patent_app_country] => US [patent_app_date] => 1997-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 15713 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838931.pdf [firstpage_image] =>[orig_patent_app_number] => 854158 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/854158
Method and apparatus for enabling a processor to access an external component through a private bus or a shared bus May 8, 1997 Issued
Array ( [id] => 4022437 [patent_doc_number] => 05987600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Exception handling in a processor that performs speculative out-of-order instruction execution' [patent_app_type] => 1 [patent_app_number] => 8/851140 [patent_app_country] => US [patent_app_date] => 1997-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8927 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987600.pdf [firstpage_image] =>[orig_patent_app_number] => 851140 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/851140
Exception handling in a processor that performs speculative out-of-order instruction execution May 4, 1997 Issued
Array ( [id] => 3877849 [patent_doc_number] => 05796966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Method and apparatus for dynamically controlling data routes through a network' [patent_app_type] => 1 [patent_app_number] => 8/850975 [patent_app_country] => US [patent_app_date] => 1997-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3953 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796966.pdf [firstpage_image] =>[orig_patent_app_number] => 850975 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/850975
Method and apparatus for dynamically controlling data routes through a network May 4, 1997 Issued
Array ( [id] => 3749798 [patent_doc_number] => 05786885 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Image processing system' [patent_app_type] => 1 [patent_app_number] => 8/840847 [patent_app_country] => US [patent_app_date] => 1997-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 2840 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/786/05786885.pdf [firstpage_image] =>[orig_patent_app_number] => 840847 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840847
Image processing system Apr 16, 1997 Issued
Array ( [id] => 3974408 [patent_doc_number] => 05937175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'PCI bus to IEEE 1394 bus translator employing pipe-lined read prefetching' [patent_app_type] => 1 [patent_app_number] => 8/826925 [patent_app_country] => US [patent_app_date] => 1997-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 15417 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937175.pdf [firstpage_image] =>[orig_patent_app_number] => 826925 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/826925
PCI bus to IEEE 1394 bus translator employing pipe-lined read prefetching Apr 7, 1997 Issued
Array ( [id] => 4042646 [patent_doc_number] => 05903767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Integrated circuit for providing supervisory functions to a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/834880 [patent_app_country] => US [patent_app_date] => 1997-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6490 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903767.pdf [firstpage_image] =>[orig_patent_app_number] => 834880 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/834880
Integrated circuit for providing supervisory functions to a microprocessor Apr 6, 1997 Issued
08/832963 ELECTRIC SYSTEM FOR PROCESSING DOMESTIC INFORMATION Apr 3, 1997 Abandoned
Array ( [id] => 4121771 [patent_doc_number] => 06023775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Fault information management system and fault information management method' [patent_app_type] => 1 [patent_app_number] => 8/829188 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 31 [patent_no_of_words] => 18479 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023775.pdf [firstpage_image] =>[orig_patent_app_number] => 829188 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829188
Fault information management system and fault information management method Mar 30, 1997 Issued
Array ( [id] => 3918223 [patent_doc_number] => 05751974 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Contention resolution for a shared access bus' [patent_app_type] => 1 [patent_app_number] => 8/827123 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1214 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751974.pdf [firstpage_image] =>[orig_patent_app_number] => 827123 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/827123
Contention resolution for a shared access bus Mar 26, 1997 Issued
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