
Robert Edward Fuller
Examiner (ID: 19273, Phone: (571)272-6300 , Office: P/3676 )
| Most Active Art Unit | 3676 |
| Art Unit(s) | 3676, 3672 |
| Total Applications | 1121 |
| Issued Applications | 829 |
| Pending Applications | 108 |
| Abandoned Applications | 206 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4100825
[patent_doc_number] => 06018782
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Flexible buffering scheme for inter-module on-chip communications'
[patent_app_type] => 1
[patent_app_number] => 8/892415
[patent_app_country] => US
[patent_app_date] => 1997-07-14
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[patent_drawing_sheets_cnt] => 5
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/018/06018782.pdf
[firstpage_image] =>[orig_patent_app_number] => 892415
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/892415 | Flexible buffering scheme for inter-module on-chip communications | Jul 13, 1997 | Issued |
Array
(
[id] => 3943461
[patent_doc_number] => 05878237
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-02
[patent_title] => 'Apparatus, method and system for a comuter CPU and memory to PCI bridge having a pluarlity of physical PCI buses'
[patent_app_type] => 1
[patent_app_number] => 8/893849
[patent_app_country] => US
[patent_app_date] => 1997-07-11
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/878/05878237.pdf
[firstpage_image] =>[orig_patent_app_number] => 893849
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/893849 | Apparatus, method and system for a comuter CPU and memory to PCI bridge having a pluarlity of physical PCI buses | Jul 10, 1997 | Issued |
Array
(
[id] => 4374520
[patent_doc_number] => 06170031
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-02
[patent_title] => 'Read/write state machines for transferring data to/from host interface in a digital data storage system'
[patent_app_type] => 1
[patent_app_number] => 8/889360
[patent_app_country] => US
[patent_app_date] => 1997-07-08
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[patent_drawing_sheets_cnt] => 10
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[firstpage_image] =>[orig_patent_app_number] => 889360
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/889360 | Read/write state machines for transferring data to/from host interface in a digital data storage system | Jul 7, 1997 | Issued |
Array
(
[id] => 4118032
[patent_doc_number] => 06098137
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Fault tolerant computer system'
[patent_app_type] => 1
[patent_app_number] => 8/882504
[patent_app_country] => US
[patent_app_date] => 1997-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[firstpage_image] =>[orig_patent_app_number] => 882504
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/882504 | Fault tolerant computer system | Jun 24, 1997 | Issued |
Array
(
[id] => 3904817
[patent_doc_number] => 05778204
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-07
[patent_title] => 'High-speed dominant mode bus for differential signals'
[patent_app_type] => 1
[patent_app_number] => 8/880252
[patent_app_country] => US
[patent_app_date] => 1997-06-23
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 880252
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/880252 | High-speed dominant mode bus for differential signals | Jun 22, 1997 | Issued |
Array
(
[id] => 4199690
[patent_doc_number] => 06021452
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Computer system capable of symmetrical processing'
[patent_app_type] => 1
[patent_app_number] => 8/879400
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[pdf_file] => patents/06/021/06021452.pdf
[firstpage_image] =>[orig_patent_app_number] => 879400
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/879400 | Computer system capable of symmetrical processing | Jun 19, 1997 | Issued |
Array
(
[id] => 4021765
[patent_doc_number] => 05987557
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Method and apparatus for implementing hardware protection domains in a system with no memory management unit (MMU)'
[patent_app_type] => 1
[patent_app_number] => 8/879124
[patent_app_country] => US
[patent_app_date] => 1997-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/05/987/05987557.pdf
[firstpage_image] =>[orig_patent_app_number] => 879124
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/879124 | Method and apparatus for implementing hardware protection domains in a system with no memory management unit (MMU) | Jun 18, 1997 | Issued |
Array
(
[id] => 4137955
[patent_doc_number] => 06073163
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Method and apparatus for enabling web-based execution of an application'
[patent_app_type] => 1
[patent_app_number] => 8/872777
[patent_app_country] => US
[patent_app_date] => 1997-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 6780
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[pdf_file] => patents/06/073/06073163.pdf
[firstpage_image] =>[orig_patent_app_number] => 872777
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/872777 | Method and apparatus for enabling web-based execution of an application | Jun 9, 1997 | Issued |
Array
(
[id] => 4002639
[patent_doc_number] => 05960180
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-28
[patent_title] => 'Host adapter integrated circuit having autoaccess pause'
[patent_app_type] => 1
[patent_app_number] => 8/869665
[patent_app_country] => US
[patent_app_date] => 1997-06-05
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[firstpage_image] =>[orig_patent_app_number] => 869665
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/869665 | Host adapter integrated circuit having autoaccess pause | Jun 4, 1997 | Issued |
Array
(
[id] => 4151473
[patent_doc_number] => 06035357
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'IC card compatible with different supply voltages, IC card system comprising the same, and IC for the IC card'
[patent_app_type] => 1
[patent_app_number] => 8/868154
[patent_app_country] => US
[patent_app_date] => 1997-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[pdf_file] => patents/06/035/06035357.pdf
[firstpage_image] =>[orig_patent_app_number] => 868154
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/868154 | IC card compatible with different supply voltages, IC card system comprising the same, and IC for the IC card | Jun 2, 1997 | Issued |
Array
(
[id] => 4057222
[patent_doc_number] => 05996037
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'System and method for arbitrating multi-function access to a system bus'
[patent_app_type] => 1
[patent_app_number] => 8/867992
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[pdf_file] => patents/05/996/05996037.pdf
[firstpage_image] =>[orig_patent_app_number] => 867992
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/867992 | System and method for arbitrating multi-function access to a system bus | Jun 2, 1997 | Issued |
Array
(
[id] => 3887564
[patent_doc_number] => 05838931
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[patent_issue_date] => 1998-11-17
[patent_title] => 'Method and apparatus for enabling a processor to access an external component through a private bus or a shared bus'
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[patent_app_number] => 8/854158
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/854158 | Method and apparatus for enabling a processor to access an external component through a private bus or a shared bus | May 8, 1997 | Issued |
Array
(
[id] => 4022437
[patent_doc_number] => 05987600
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[patent_issue_date] => 1999-11-16
[patent_title] => 'Exception handling in a processor that performs speculative out-of-order instruction execution'
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Array
(
[id] => 3877849
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[patent_title] => 'Method and apparatus for dynamically controlling data routes through a network'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/850975 | Method and apparatus for dynamically controlling data routes through a network | May 4, 1997 | Issued |
Array
(
[id] => 3749798
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[patent_title] => 'Image processing system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/840847 | Image processing system | Apr 16, 1997 | Issued |
Array
(
[id] => 3974408
[patent_doc_number] => 05937175
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[patent_issue_date] => 1999-08-10
[patent_title] => 'PCI bus to IEEE 1394 bus translator employing pipe-lined read prefetching'
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[patent_app_number] => 8/826925
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/826925 | PCI bus to IEEE 1394 bus translator employing pipe-lined read prefetching | Apr 7, 1997 | Issued |
Array
(
[id] => 4042646
[patent_doc_number] => 05903767
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-11
[patent_title] => 'Integrated circuit for providing supervisory functions to a microprocessor'
[patent_app_type] => 1
[patent_app_number] => 8/834880
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/834880 | Integrated circuit for providing supervisory functions to a microprocessor | Apr 6, 1997 | Issued |
| 08/832963 | ELECTRIC SYSTEM FOR PROCESSING DOMESTIC INFORMATION | Apr 3, 1997 | Abandoned |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/829188 | Fault information management system and fault information management method | Mar 30, 1997 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/827123 | Contention resolution for a shared access bus | Mar 26, 1997 | Issued |