
Robert Edward Fuller
Examiner (ID: 19273, Phone: (571)272-6300 , Office: P/3676 )
| Most Active Art Unit | 3676 |
| Art Unit(s) | 3676, 3672 |
| Total Applications | 1121 |
| Issued Applications | 829 |
| Pending Applications | 108 |
| Abandoned Applications | 206 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3741565
[patent_doc_number] => 05671376
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-23
[patent_title] => 'Universal SCSI electrical interface system'
[patent_app_type] => 1
[patent_app_number] => 8/646080
[patent_app_country] => US
[patent_app_date] => 1996-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 5144
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/671/05671376.pdf
[firstpage_image] =>[orig_patent_app_number] => 646080
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/646080 | Universal SCSI electrical interface system | May 6, 1996 | Issued |
Array
(
[id] => 4064420
[patent_doc_number] => 05870548
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Method and apparatus for altering sent electronic mail messages'
[patent_app_type] => 1
[patent_app_number] => 8/628440
[patent_app_country] => US
[patent_app_date] => 1996-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 22
[patent_no_of_words] => 10877
[patent_no_of_claims] => 49
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/870/05870548.pdf
[firstpage_image] =>[orig_patent_app_number] => 628440
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/628440 | Method and apparatus for altering sent electronic mail messages | Apr 4, 1996 | Issued |
Array
(
[id] => 4100864
[patent_doc_number] => 06018785
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Interrupt-generating hardware semaphore'
[patent_app_type] => 1
[patent_app_number] => 8/617018
[patent_app_country] => US
[patent_app_date] => 1996-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6591
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/018/06018785.pdf
[firstpage_image] =>[orig_patent_app_number] => 617018
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/617018 | Interrupt-generating hardware semaphore | Mar 17, 1996 | Issued |
Array
(
[id] => 3802514
[patent_doc_number] => 05822553
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Multiple parallel digital data stream channel controller architecture'
[patent_app_type] => 1
[patent_app_number] => 8/614729
[patent_app_country] => US
[patent_app_date] => 1996-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 23464
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/822/05822553.pdf
[firstpage_image] =>[orig_patent_app_number] => 614729
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/614729 | Multiple parallel digital data stream channel controller architecture | Mar 12, 1996 | Issued |
Array
(
[id] => 3716221
[patent_doc_number] => 05675748
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-07
[patent_title] => 'Method and apparatus for automatically configuring computer system hardware and software'
[patent_app_type] => 1
[patent_app_number] => 8/608326
[patent_app_country] => US
[patent_app_date] => 1996-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 11475
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 306
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/675/05675748.pdf
[firstpage_image] =>[orig_patent_app_number] => 608326
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/608326 | Method and apparatus for automatically configuring computer system hardware and software | Mar 7, 1996 | Issued |
Array
(
[id] => 3829734
[patent_doc_number] => 05812792
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Use of video DRAM for memory storage in a local area network port of a switching hub'
[patent_app_type] => 1
[patent_app_number] => 8/606555
[patent_app_country] => US
[patent_app_date] => 1996-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 25483
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/812/05812792.pdf
[firstpage_image] =>[orig_patent_app_number] => 606555
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/606555 | Use of video DRAM for memory storage in a local area network port of a switching hub | Feb 25, 1996 | Issued |
Array
(
[id] => 3873055
[patent_doc_number] => 05768605
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-16
[patent_title] => 'Method and apparatus for power management of a PCMCIA card'
[patent_app_type] => 1
[patent_app_number] => 8/603500
[patent_app_country] => US
[patent_app_date] => 1996-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 3101
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/768/05768605.pdf
[firstpage_image] =>[orig_patent_app_number] => 603500
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/603500 | Method and apparatus for power management of a PCMCIA card | Feb 19, 1996 | Issued |
Array
(
[id] => 3660777
[patent_doc_number] => 05630147
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-13
[patent_title] => 'System management shadow port'
[patent_app_type] => 1
[patent_app_number] => 8/601697
[patent_app_country] => US
[patent_app_date] => 1996-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3735
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/630/05630147.pdf
[firstpage_image] =>[orig_patent_app_number] => 601697
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/601697 | System management shadow port | Feb 14, 1996 | Issued |
Array
(
[id] => 3859156
[patent_doc_number] => 05745770
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-28
[patent_title] => 'Method and apparatus for servicing simultaneous I/O trap and debug traps in a microprocessor'
[patent_app_type] => 1
[patent_app_number] => 8/595187
[patent_app_country] => US
[patent_app_date] => 1996-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6153
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/745/05745770.pdf
[firstpage_image] =>[orig_patent_app_number] => 595187
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/595187 | Method and apparatus for servicing simultaneous I/O trap and debug traps in a microprocessor | Jan 31, 1996 | Issued |
| 08/588285 | ENHANCED POWER MANAGEMENT UNIT (PMU) IN MULTIPROCESSOR CHIP WITH ON BOARD SDL/PLL | Jan 17, 1996 | Abandoned |
Array
(
[id] => 4103541
[patent_doc_number] => 06026456
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'System utilizing distributed on-chip termination'
[patent_app_type] => 1
[patent_app_number] => 8/573568
[patent_app_country] => US
[patent_app_date] => 1995-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4659
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/026/06026456.pdf
[firstpage_image] =>[orig_patent_app_number] => 573568
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/573568 | System utilizing distributed on-chip termination | Dec 14, 1995 | Issued |
Array
(
[id] => 3837032
[patent_doc_number] => 05790870
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Bus error handler for PERR# and SERR# on dual PCI bus system'
[patent_app_type] => 1
[patent_app_number] => 8/573030
[patent_app_country] => US
[patent_app_date] => 1995-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6060
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/790/05790870.pdf
[firstpage_image] =>[orig_patent_app_number] => 573030
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/573030 | Bus error handler for PERR# and SERR# on dual PCI bus system | Dec 14, 1995 | Issued |
Array
(
[id] => 290382
[patent_doc_number] => 07549007
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-06-16
[patent_title] => 'Portable computer having an interface for direct connection to a mobile telephone'
[patent_app_type] => utility
[patent_app_number] => 08/568777
[patent_app_country] => US
[patent_app_date] => 1995-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 79
[patent_figures_cnt] => 175
[patent_no_of_words] => 20711
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/549/07549007.pdf
[firstpage_image] =>[orig_patent_app_number] => 08568777
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/568777 | Portable computer having an interface for direct connection to a mobile telephone | Dec 6, 1995 | Issued |
Array
(
[id] => 535175
[patent_doc_number] => 07194646
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-03-20
[patent_title] => 'Real-time thermal management for computers'
[patent_app_type] => utility
[patent_app_number] => 08/568904
[patent_app_country] => US
[patent_app_date] => 1995-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 10837
[patent_no_of_claims] => 55
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/194/07194646.pdf
[firstpage_image] =>[orig_patent_app_number] => 08568904
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/568904 | Real-time thermal management for computers | Dec 6, 1995 | Issued |
Array
(
[id] => 3529968
[patent_doc_number] => 05577196
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-19
[patent_title] => 'Intelligent digital signal hitless protection switch'
[patent_app_type] => 1
[patent_app_number] => 8/565223
[patent_app_country] => US
[patent_app_date] => 1995-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 7048
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/577/05577196.pdf
[firstpage_image] =>[orig_patent_app_number] => 565223
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/565223 | Intelligent digital signal hitless protection switch | Nov 29, 1995 | Issued |
Array
(
[id] => 3857790
[patent_doc_number] => 05848276
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'High speed, direct register access operation for parallel processing units'
[patent_app_type] => 1
[patent_app_number] => 8/554671
[patent_app_country] => US
[patent_app_date] => 1995-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3272
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 224
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/848/05848276.pdf
[firstpage_image] =>[orig_patent_app_number] => 554671
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/554671 | High speed, direct register access operation for parallel processing units | Nov 7, 1995 | Issued |
| 08/539112 | METHOD FOR LOWERING POWER CONSUMPTION IN A COMPUTING DEVICE | Oct 3, 1995 | Abandoned |
Array
(
[id] => 3895081
[patent_doc_number] => 05799194
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-25
[patent_title] => 'Communication interface circuit having network connection detection capability'
[patent_app_type] => 1
[patent_app_number] => 8/534954
[patent_app_country] => US
[patent_app_date] => 1995-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4867
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/799/05799194.pdf
[firstpage_image] =>[orig_patent_app_number] => 534954
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/534954 | Communication interface circuit having network connection detection capability | Sep 27, 1995 | Issued |
Array
(
[id] => 3674288
[patent_doc_number] => 05657456
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Semiconductor process power supply voltage and temperature compensated integrated system bus driver rise and fall time'
[patent_app_type] => 1
[patent_app_number] => 8/527298
[patent_app_country] => US
[patent_app_date] => 1995-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 27
[patent_no_of_words] => 17453
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/657/05657456.pdf
[firstpage_image] =>[orig_patent_app_number] => 527298
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/527298 | Semiconductor process power supply voltage and temperature compensated integrated system bus driver rise and fall time | Sep 11, 1995 | Issued |
Array
(
[id] => 3778489
[patent_doc_number] => 05845082
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-01
[patent_title] => 'Distributed system having an improved method and apparatus for checkpoint taking'
[patent_app_type] => 1
[patent_app_number] => 8/518395
[patent_app_country] => US
[patent_app_date] => 1995-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 36
[patent_no_of_words] => 22544
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 15
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/845/05845082.pdf
[firstpage_image] =>[orig_patent_app_number] => 518395
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/518395 | Distributed system having an improved method and apparatus for checkpoint taking | Aug 14, 1995 | Issued |