Search

Robert Edward Fuller

Examiner (ID: 19273, Phone: (571)272-6300 , Office: P/3676 )

Most Active Art Unit
3676
Art Unit(s)
3676, 3672
Total Applications
1121
Issued Applications
829
Pending Applications
108
Abandoned Applications
206

Applications

Application numberTitle of the applicationFiling DateStatus
08/301632 IMAGE PROCESSING SYSTEM Sep 6, 1994 Abandoned
Array ( [id] => 3612930 [patent_doc_number] => 05560023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Automatic backup system for advanced power management' [patent_app_type] => 1 [patent_app_number] => 8/301943 [patent_app_country] => US [patent_app_date] => 1994-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 54 [patent_no_of_words] => 37479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/560/05560023.pdf [firstpage_image] =>[orig_patent_app_number] => 301943 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/301943
Automatic backup system for advanced power management Sep 6, 1994 Issued
Array ( [id] => 3637097 [patent_doc_number] => 05603038 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Automatic restoration of user options after power loss' [patent_app_type] => 1 [patent_app_number] => 8/302066 [patent_app_country] => US [patent_app_date] => 1994-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 54 [patent_no_of_words] => 38062 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/603/05603038.pdf [firstpage_image] =>[orig_patent_app_number] => 302066 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/302066
Automatic restoration of user options after power loss Sep 6, 1994 Issued
08/302157 LOW POWER RING DETECT FOR COMPUTER SYSTEM WAKEUP Sep 6, 1994 Abandoned
08/298873 SYSTEM AND METHOD FOR COMMUNICATING BETWEEN DEVICES Aug 30, 1994 Abandoned
08/293517 METHOD AND APPARATUS FOR HIGH-SPEED COMMUNICATION BETWEEN COMPUTER AND PERIPHERALS Aug 18, 1994 Abandoned
Array ( [id] => 3758262 [patent_doc_number] => 05754798 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Computer system with function for controlling system configuration and power supply status data' [patent_app_type] => 1 [patent_app_number] => 8/291942 [patent_app_country] => US [patent_app_date] => 1994-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 18235 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754798.pdf [firstpage_image] =>[orig_patent_app_number] => 291942 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/291942
Computer system with function for controlling system configuration and power supply status data Aug 16, 1994 Issued
Array ( [id] => 3694887 [patent_doc_number] => 05634060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Method and apparatus for high-speed efficient bi-directional communication between multiple processor over a common bus' [patent_app_type] => 1 [patent_app_number] => 8/287878 [patent_app_country] => US [patent_app_date] => 1994-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 12537 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/634/05634060.pdf [firstpage_image] =>[orig_patent_app_number] => 287878 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/287878
Method and apparatus for high-speed efficient bi-directional communication between multiple processor over a common bus Aug 8, 1994 Issued
Array ( [id] => 3676616 [patent_doc_number] => 05598542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Method and apparatus for bus arbitration in a multiple bus information handling system using time slot assignment values' [patent_app_type] => 1 [patent_app_number] => 8/287213 [patent_app_country] => US [patent_app_date] => 1994-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8557 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598542.pdf [firstpage_image] =>[orig_patent_app_number] => 287213 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/287213
Method and apparatus for bus arbitration in a multiple bus information handling system using time slot assignment values Aug 7, 1994 Issued
Array ( [id] => 3599971 [patent_doc_number] => 05553252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Device for controlling data transfer between chips via a bus' [patent_app_type] => 1 [patent_app_number] => 8/284873 [patent_app_country] => US [patent_app_date] => 1994-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8875 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/553/05553252.pdf [firstpage_image] =>[orig_patent_app_number] => 284873 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/284873
Device for controlling data transfer between chips via a bus Aug 1, 1994 Issued
08/280622 METHOD TO AUTOMATICALLY DETECT THE INTERRUPT CHANNEL STATUS OF AN ADD-ON CARD Jul 25, 1994 Abandoned
08/278293 CONTENTION RESOLUTION METHOD FOR A SHARED ACCESS BUS Jul 20, 1994 Abandoned
08/277598 METHOD FOR INITIALIZING AN ARRAY OF CONFIGURABLE COMPONENTS Jul 19, 1994 Abandoned
Array ( [id] => 3893880 [patent_doc_number] => 05729723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Data processing unit' [patent_app_type] => 1 [patent_app_number] => 8/275347 [patent_app_country] => US [patent_app_date] => 1994-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 12825 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 617 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729723.pdf [firstpage_image] =>[orig_patent_app_number] => 275347 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/275347
Data processing unit Jul 14, 1994 Issued
08/274933 SYSTEM AND METHOD FOR PROVIDING CENTRALIZED BACKUP POWER IN A COMPUTER SYSTEM Jul 13, 1994 Abandoned
08/261973 DATA BUS CONTROLLER HAVING A LEVEL SETTING CIRCUIT Jun 16, 1994 Abandoned
Array ( [id] => 3566838 [patent_doc_number] => 05574922 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Processor with sequences of processor instructions for locked memory updates' [patent_app_type] => 1 [patent_app_number] => 8/261168 [patent_app_country] => US [patent_app_date] => 1994-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 32 [patent_no_of_words] => 17357 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574922.pdf [firstpage_image] =>[orig_patent_app_number] => 261168 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/261168
Processor with sequences of processor instructions for locked memory updates Jun 16, 1994 Issued
Array ( [id] => 4297956 [patent_doc_number] => 06282572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Providing a master device with slave device capability information' [patent_app_type] => 1 [patent_app_number] => 8/237988 [patent_app_country] => US [patent_app_date] => 1994-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5961 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282572.pdf [firstpage_image] =>[orig_patent_app_number] => 237988 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/237988
Providing a master device with slave device capability information May 3, 1994 Issued
Array ( [id] => 3672820 [patent_doc_number] => 05649127 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Method and apparatus for packing digital data' [patent_app_type] => 1 [patent_app_number] => 8/238273 [patent_app_country] => US [patent_app_date] => 1994-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 7230 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649127.pdf [firstpage_image] =>[orig_patent_app_number] => 238273 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/238273
Method and apparatus for packing digital data May 3, 1994 Issued
Array ( [id] => 3511215 [patent_doc_number] => 05533204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-02 [patent_title] => 'Split transaction protocol for the peripheral component interconnect bus' [patent_app_type] => 1 [patent_app_number] => 8/229233 [patent_app_country] => US [patent_app_date] => 1994-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7378 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/533/05533204.pdf [firstpage_image] =>[orig_patent_app_number] => 229233 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/229233
Split transaction protocol for the peripheral component interconnect bus Apr 17, 1994 Issued
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