Search

Robert G. Bachner

Examiner (ID: 7375, Phone: (571)270-3888 , Office: P/2898 )

Most Active Art Unit
2898
Art Unit(s)
2813, 2898
Total Applications
1219
Issued Applications
1068
Pending Applications
78
Abandoned Applications
110

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16692132 [patent_doc_number] => 20210074611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/786416 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786416 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/786416
Semiconductor device Feb 9, 2020 Issued
Array ( [id] => 16566912 [patent_doc_number] => 10892289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Optical sensors including a light-impeding pattern [patent_app_type] => utility [patent_app_number] => 16/784308 [patent_app_country] => US [patent_app_date] => 2020-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 10598 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784308 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/784308
Optical sensors including a light-impeding pattern Feb 6, 2020 Issued
Array ( [id] => 16995392 [patent_doc_number] => 20210233812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => LARGE GRAIN COPPER INTERCONNECT LINES FOR MRAM [patent_app_type] => utility [patent_app_number] => 16/773939 [patent_app_country] => US [patent_app_date] => 2020-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16773939 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/773939
Large grain copper interconnect lines for MRAM Jan 26, 2020 Issued
Array ( [id] => 17421398 [patent_doc_number] => 11254840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Polishing slurry and method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 16/750060 [patent_app_country] => US [patent_app_date] => 2020-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7642 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16750060 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/750060
Polishing slurry and method of manufacturing semiconductor device Jan 22, 2020 Issued
Array ( [id] => 18205676 [patent_doc_number] => 11588084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Method and structure for die bonding using energy beam [patent_app_type] => utility [patent_app_number] => 16/748860 [patent_app_country] => US [patent_app_date] => 2020-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 33 [patent_no_of_words] => 10864 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16748860 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/748860
Method and structure for die bonding using energy beam Jan 21, 2020 Issued
Array ( [id] => 15910113 [patent_doc_number] => 20200154578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => CIRCUIT SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/746968 [patent_app_country] => US [patent_app_date] => 2020-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5775 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746968 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/746968
Circuit substrate Jan 19, 2020 Issued
Array ( [id] => 17343438 [patent_doc_number] => 20220009769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => MEMS SENSOR AS WELL AS METHOD FOR OPERATING A MEMS SENSOR [patent_app_type] => utility [patent_app_number] => 17/291864 [patent_app_country] => US [patent_app_date] => 2020-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17291864 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/291864
MEMS sensor as well as method for operating a mems sensor Jan 19, 2020 Issued
Array ( [id] => 16981498 [patent_doc_number] => 20210225735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 16/746017 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746017 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/746017
Semiconductor device and method Jan 16, 2020 Issued
Array ( [id] => 16226292 [patent_doc_number] => 20200251409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/744743 [patent_app_country] => US [patent_app_date] => 2020-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744743 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/744743
Semiconductor device with semiconductor element and electrodes on different surfaces Jan 15, 2020 Issued
Array ( [id] => 17353305 [patent_doc_number] => 11227952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Integrated circuit devices and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/743206 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 10265 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743206 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/743206
Integrated circuit devices and methods of manufacturing the same Jan 14, 2020 Issued
Array ( [id] => 16966187 [patent_doc_number] => 20210217686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => LEADFRAME WITH DELAMINATION RESISTANT FEATURE [patent_app_type] => utility [patent_app_number] => 16/743067 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3269 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743067 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/743067
Leadframe with delamination resistant feature Jan 14, 2020 Issued
Array ( [id] => 16966366 [patent_doc_number] => 20210217865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => DUAL BIT MEMORY DEVICE WITH TRIPLE GATE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/741769 [patent_app_country] => US [patent_app_date] => 2020-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741769 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/741769
Dual bit memory device with triple gate structure Jan 13, 2020 Issued
Array ( [id] => 15905991 [patent_doc_number] => 20200152516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => Semiconductor Device and Method of Manufacture [patent_app_type] => utility [patent_app_number] => 16/742630 [patent_app_country] => US [patent_app_date] => 2020-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16742630 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/742630
Semiconductor device and method of manufacture Jan 13, 2020 Issued
Array ( [id] => 15873569 [patent_doc_number] => 20200144188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => POWER SEMICONDUCTOR MODULE WITH DIMPLES IN METALLIZATION LAYER BELOW FOOT OF TERMINAL [patent_app_type] => utility [patent_app_number] => 16/737356 [patent_app_country] => US [patent_app_date] => 2020-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16737356 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/737356
Power semiconductor module with dimples in metallization layer below foot of terminal Jan 7, 2020 Issued
Array ( [id] => 15873307 [patent_doc_number] => 20200144057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => Gate Stack Designs for Analog and Logic Devices in Dual Channel Si/SiGe CMOS [patent_app_type] => utility [patent_app_number] => 16/737539 [patent_app_country] => US [patent_app_date] => 2020-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16737539 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/737539
Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS Jan 7, 2020 Issued
Array ( [id] => 16021331 [patent_doc_number] => 20200185509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => METHODS, APPARATUS AND SYSTEM FOR A SELF-ALIGNED GATE CUT ON A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/730712 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730712 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/730712
Methods, apparatus and system for a self-aligned gate cut on a semiconductor device Dec 29, 2019 Issued
Array ( [id] => 16106795 [patent_doc_number] => 20200205420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => BAKING OVEN [patent_app_type] => utility [patent_app_number] => 16/726811 [patent_app_country] => US [patent_app_date] => 2019-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16726811 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/726811
BAKING OVEN Dec 23, 2019 Abandoned
Array ( [id] => 16761996 [patent_doc_number] => 20210107577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => ZERO MOMENT POINT JITTER PROCESSING METHOD AND APPARATUS AND ROBOT USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/724413 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724413 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724413
Zero moment point jitter processing method and apparatus and robot using the same Dec 22, 2019 Issued
Array ( [id] => 16707631 [patent_doc_number] => 10957575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Method for connecting a buried interconnect rail and a semiconductor fin in an integrated circuit chip [patent_app_type] => utility [patent_app_number] => 16/718624 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4081 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16718624 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/718624
Method for connecting a buried interconnect rail and a semiconductor fin in an integrated circuit chip Dec 17, 2019 Issued
Array ( [id] => 17683440 [patent_doc_number] => 11367705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Method for packaging semiconductor dies [patent_app_type] => utility [patent_app_number] => 16/719680 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 4733 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719680 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/719680
Method for packaging semiconductor dies Dec 17, 2019 Issued
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