Search

Robert G. Santos

Examiner (ID: 11440, Phone: (571)272-7048 , Office: P/3673 )

Most Active Art Unit
3673
Art Unit(s)
3633, 3628, 3673, 3508
Total Applications
2492
Issued Applications
1855
Pending Applications
190
Abandoned Applications
474

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5073418 [patent_doc_number] => 20070013393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'TEST PROBE AND TESTER, METHOD FOR MANUFACTURING THE TEST PROBE' [patent_app_type] => utility [patent_app_number] => 11/532654 [patent_app_country] => US [patent_app_date] => 2006-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7172 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20070013393.pdf [firstpage_image] =>[orig_patent_app_number] => 11532654 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/532654
TEST PROBE AND TESTER, METHOD FOR MANUFACTURING THE TEST PROBE Sep 17, 2006 Abandoned
Array ( [id] => 5141906 [patent_doc_number] => 20070004122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Method for fabricating semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/518882 [patent_app_country] => US [patent_app_date] => 2006-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8300 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20070004122.pdf [firstpage_image] =>[orig_patent_app_number] => 11518882 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/518882
Method for fabricating semiconductor memory device Sep 11, 2006 Abandoned
Array ( [id] => 4485745 [patent_doc_number] => 07883985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Chip and multi-chip semiconductor device using the chip, and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 11/518274 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 10643 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/883/07883985.pdf [firstpage_image] =>[orig_patent_app_number] => 11518274 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/518274
Chip and multi-chip semiconductor device using the chip, and method for manufacturing same Sep 10, 2006 Issued
Array ( [id] => 4582706 [patent_doc_number] => 07851294 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-14 [patent_title] => 'Nanotube memory cell with floating gate based on passivated nanoparticles and manufacturing process thereof' [patent_app_type] => utility [patent_app_number] => 11/518385 [patent_app_country] => US [patent_app_date] => 2006-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3773 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/851/07851294.pdf [firstpage_image] =>[orig_patent_app_number] => 11518385 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/518385
Nanotube memory cell with floating gate based on passivated nanoparticles and manufacturing process thereof Sep 7, 2006 Issued
Array ( [id] => 5202445 [patent_doc_number] => 20070023924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/516703 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7931 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20070023924.pdf [firstpage_image] =>[orig_patent_app_number] => 11516703 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/516703
Semiconductor device and method of manufacturing the same Sep 6, 2006 Abandoned
Array ( [id] => 557796 [patent_doc_number] => 07470610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-30 [patent_title] => 'Method of fabricating organic electroluminescent devices' [patent_app_type] => utility [patent_app_number] => 11/517726 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4458 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/470/07470610.pdf [firstpage_image] =>[orig_patent_app_number] => 11517726 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/517726
Method of fabricating organic electroluminescent devices Sep 6, 2006 Issued
Array ( [id] => 42544 [patent_doc_number] => 07781259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Method of manufacturing a semiconductor using a rigid substrate' [patent_app_type] => utility [patent_app_number] => 11/516584 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 7331 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/781/07781259.pdf [firstpage_image] =>[orig_patent_app_number] => 11516584 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/516584
Method of manufacturing a semiconductor using a rigid substrate Sep 6, 2006 Issued
Array ( [id] => 8294895 [patent_doc_number] => 08222683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Semiconductor device and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/515875 [patent_app_country] => US [patent_app_date] => 2006-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 69 [patent_no_of_words] => 19275 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11515875 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/515875
Semiconductor device and its manufacturing method Sep 5, 2006 Issued
Array ( [id] => 7689366 [patent_doc_number] => 20070105332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'INTEGRATED CIRCUIT CAPACITOR HAVING ANTIREFLECTIVE DIELECTRIC' [patent_app_type] => utility [patent_app_number] => 11/470023 [patent_app_country] => US [patent_app_date] => 2006-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3934 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20070105332.pdf [firstpage_image] =>[orig_patent_app_number] => 11470023 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/470023
Integrated circuit capacitor having antireflective dielectric Sep 4, 2006 Issued
Array ( [id] => 4820864 [patent_doc_number] => 20080122119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'METHOD AND APPARATUS FOR CREATING RFID DEVICES USING MASKING TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 11/469313 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7292 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122119.pdf [firstpage_image] =>[orig_patent_app_number] => 11469313 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/469313
METHOD AND APPARATUS FOR CREATING RFID DEVICES USING MASKING TECHNIQUES Aug 30, 2006 Abandoned
Array ( [id] => 5602444 [patent_doc_number] => 20060292789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'STRUCTURE AND METHOD FOR COLLAR SELF-ALIGNED TO BURIED PLATE' [patent_app_type] => utility [patent_app_number] => 11/468543 [patent_app_country] => US [patent_app_date] => 2006-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3954 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20060292789.pdf [firstpage_image] =>[orig_patent_app_number] => 11468543 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/468543
STRUCTURE AND METHOD FOR COLLAR SELF-ALIGNED TO BURIED PLATE Aug 29, 2006 Abandoned
Array ( [id] => 8270242 [patent_doc_number] => 08211748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Systems and methods for low profile die package' [patent_app_type] => utility [patent_app_number] => 11/511175 [patent_app_country] => US [patent_app_date] => 2006-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1990 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11511175 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/511175
Systems and methods for low profile die package Aug 27, 2006 Issued
Array ( [id] => 32507 [patent_doc_number] => 07790558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Method and apparatus for increase strain effect in a transistor channel' [patent_app_type] => utility [patent_app_number] => 11/465663 [patent_app_country] => US [patent_app_date] => 2006-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3143 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/790/07790558.pdf [firstpage_image] =>[orig_patent_app_number] => 11465663 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465663
Method and apparatus for increase strain effect in a transistor channel Aug 17, 2006 Issued
Array ( [id] => 4999917 [patent_doc_number] => 20070042551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Method of manufacturing a trench transistor having a heavy body region' [patent_app_type] => utility [patent_app_number] => 11/503506 [patent_app_country] => US [patent_app_date] => 2006-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4803 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20070042551.pdf [firstpage_image] =>[orig_patent_app_number] => 11503506 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/503506
Method of manufacturing a trench transistor having a heavy body region Aug 9, 2006 Issued
Array ( [id] => 5205184 [patent_doc_number] => 20070026666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Method of forming metal line on semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/495386 [patent_app_country] => US [patent_app_date] => 2006-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20070026666.pdf [firstpage_image] =>[orig_patent_app_number] => 11495386 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/495386
Method of forming metal line on semiconductor device Jul 26, 2006 Abandoned
Array ( [id] => 5733002 [patent_doc_number] => 20060258119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Memory array buried digit line' [patent_app_type] => utility [patent_app_number] => 11/491461 [patent_app_country] => US [patent_app_date] => 2006-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20060258119.pdf [firstpage_image] =>[orig_patent_app_number] => 11491461 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/491461
Memory array buried digit line Jul 20, 2006 Issued
Array ( [id] => 5733001 [patent_doc_number] => 20060258118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Memory array buried digit line' [patent_app_type] => utility [patent_app_number] => 11/490619 [patent_app_country] => US [patent_app_date] => 2006-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20060258118.pdf [firstpage_image] =>[orig_patent_app_number] => 11490619 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/490619
Memory array buried digit line Jul 20, 2006 Issued
Array ( [id] => 315167 [patent_doc_number] => 07525137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'TFT mask ROM and method for making same' [patent_app_type] => utility [patent_app_number] => 11/484757 [patent_app_country] => US [patent_app_date] => 2006-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7935 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/525/07525137.pdf [firstpage_image] =>[orig_patent_app_number] => 11484757 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/484757
TFT mask ROM and method for making same Jul 11, 2006 Issued
Array ( [id] => 295961 [patent_doc_number] => 07541230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Method and apparatus for crystallizing semiconductor with laser beams' [patent_app_type] => utility [patent_app_number] => 11/483897 [patent_app_country] => US [patent_app_date] => 2006-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 29 [patent_no_of_words] => 12061 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/541/07541230.pdf [firstpage_image] =>[orig_patent_app_number] => 11483897 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/483897
Method and apparatus for crystallizing semiconductor with laser beams Jul 9, 2006 Issued
Array ( [id] => 5154463 [patent_doc_number] => 20070037346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Rapid thermal annealing of targeted thin film layers' [patent_app_type] => utility [patent_app_number] => 11/479716 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9514 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20070037346.pdf [firstpage_image] =>[orig_patent_app_number] => 11479716 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/479716
Rapid thermal annealing of targeted thin film layers Jun 29, 2006 Abandoned
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