
Robert G. Santos
Examiner (ID: 11440, Phone: (571)272-7048 , Office: P/3673 )
| Most Active Art Unit | 3673 |
| Art Unit(s) | 3633, 3628, 3673, 3508 |
| Total Applications | 2492 |
| Issued Applications | 1855 |
| Pending Applications | 190 |
| Abandoned Applications | 474 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5655948
[patent_doc_number] => 20060141684
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-29
[patent_title] => 'Polysilicon film, thin film transistor using the same, and method for forming the same'
[patent_app_type] => utility
[patent_app_number] => 11/314004
[patent_app_country] => US
[patent_app_date] => 2005-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2723
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20060141684.pdf
[firstpage_image] =>[orig_patent_app_number] => 11314004
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/314004 | Polysilicon film, thin film transistor using the same, and method for forming the same | Dec 21, 2005 | Issued |
Array
(
[id] => 5649115
[patent_doc_number] => 20060134850
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-22
[patent_title] => 'Method of manufacturing a high voltage semiconductor device including a deep well and a gate oxide layer simultaneously'
[patent_app_type] => utility
[patent_app_number] => 11/313693
[patent_app_country] => US
[patent_app_date] => 2005-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1211
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0134/20060134850.pdf
[firstpage_image] =>[orig_patent_app_number] => 11313693
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/313693 | Method of manufacturing a high voltage semiconductor device including a deep well and a gate oxide layer simultaneously | Dec 21, 2005 | Issued |
Array
(
[id] => 5652734
[patent_doc_number] => 20060138469
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-29
[patent_title] => 'Semiconductor device and fabricating method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/314414
[patent_app_country] => US
[patent_app_date] => 2005-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2036
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0138/20060138469.pdf
[firstpage_image] =>[orig_patent_app_number] => 11314414
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/314414 | Semiconductor device and fabricating method thereof | Dec 21, 2005 | Abandoned |
Array
(
[id] => 5596438
[patent_doc_number] => 20060160355
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-20
[patent_title] => 'Semiconductor device with a metal line and method of forming the same'
[patent_app_type] => utility
[patent_app_number] => 11/313723
[patent_app_country] => US
[patent_app_date] => 2005-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 1972
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0160/20060160355.pdf
[firstpage_image] =>[orig_patent_app_number] => 11313723
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/313723 | Semiconductor device with a metal line and method of forming the same | Dec 21, 2005 | Issued |
Array
(
[id] => 5655983
[patent_doc_number] => 20060141719
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-29
[patent_title] => 'Method of fabricating semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/312504
[patent_app_country] => US
[patent_app_date] => 2005-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2032
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20060141719.pdf
[firstpage_image] =>[orig_patent_app_number] => 11312504
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/312504 | Method of fabricating semiconductor device | Dec 20, 2005 | Abandoned |
Array
(
[id] => 899869
[patent_doc_number] => 07338855
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-03-04
[patent_title] => 'Method for fabricating semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/312594
[patent_app_country] => US
[patent_app_date] => 2005-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 1156
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/338/07338855.pdf
[firstpage_image] =>[orig_patent_app_number] => 11312594
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/312594 | Method for fabricating semiconductor device | Dec 20, 2005 | Issued |
Array
(
[id] => 5649144
[patent_doc_number] => 20060134879
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-22
[patent_title] => 'Methods of manufacturing a metal-insulator-metal capacitor'
[patent_app_type] => utility
[patent_app_number] => 11/314293
[patent_app_country] => US
[patent_app_date] => 2005-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2374
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0134/20060134879.pdf
[firstpage_image] =>[orig_patent_app_number] => 11314293
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/314293 | Methods of manufacturing a metal-insulator-metal capacitor | Dec 20, 2005 | Issued |
Array
(
[id] => 5656045
[patent_doc_number] => 20060141781
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-29
[patent_title] => 'Method for forming metal line of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/312353
[patent_app_country] => US
[patent_app_date] => 2005-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2233
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20060141781.pdf
[firstpage_image] =>[orig_patent_app_number] => 11312353
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/312353 | Method for forming metal line of semiconductor device | Dec 20, 2005 | Issued |
Array
(
[id] => 5120035
[patent_doc_number] => 20070141749
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-21
[patent_title] => 'Die attachment method for LED chip and structure thereof'
[patent_app_type] => utility
[patent_app_number] => 11/311243
[patent_app_country] => US
[patent_app_date] => 2005-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1250
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20070141749.pdf
[firstpage_image] =>[orig_patent_app_number] => 11311243
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/311243 | Die attachment method for LED chip and structure thereof | Dec 19, 2005 | Abandoned |
Array
(
[id] => 113748
[patent_doc_number] => 07714355
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-05-11
[patent_title] => 'Method of controlling the breakdown voltage of BSCRs and BJT clamps'
[patent_app_type] => utility
[patent_app_number] => 11/312704
[patent_app_country] => US
[patent_app_date] => 2005-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1237
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/714/07714355.pdf
[firstpage_image] =>[orig_patent_app_number] => 11312704
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/312704 | Method of controlling the breakdown voltage of BSCRs and BJT clamps | Dec 19, 2005 | Issued |
Array
(
[id] => 5120030
[patent_doc_number] => 20070141744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-21
[patent_title] => 'Method of fabricating a low, dark-current germanium-on-silicon pin photo detector'
[patent_app_type] => utility
[patent_app_number] => 11/312967
[patent_app_country] => US
[patent_app_date] => 2005-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1676
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20070141744.pdf
[firstpage_image] =>[orig_patent_app_number] => 11312967
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/312967 | Method of fabricating a low, dark-current germanium-on-silicon pin photo detector | Dec 18, 2005 | Issued |
Array
(
[id] => 5683036
[patent_doc_number] => 20060199306
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-07
[patent_title] => 'CHIP STRUCTURE AND MANUFACTURING PROCESS THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/306054
[patent_app_country] => US
[patent_app_date] => 2005-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2411
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0199/20060199306.pdf
[firstpage_image] =>[orig_patent_app_number] => 11306054
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/306054 | CHIP STRUCTURE AND MANUFACTURING PROCESS THEREOF | Dec 14, 2005 | Abandoned |
Array
(
[id] => 7503385
[patent_doc_number] => 08034719
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-10-11
[patent_title] => 'Method of fabricating high aspect ratio metal structures'
[patent_app_type] => utility
[patent_app_number] => 11/311584
[patent_app_country] => US
[patent_app_date] => 2005-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 11
[patent_no_of_words] => 2774
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/034/08034719.pdf
[firstpage_image] =>[orig_patent_app_number] => 11311584
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/311584 | Method of fabricating high aspect ratio metal structures | Dec 7, 2005 | Issued |
Array
(
[id] => 5747912
[patent_doc_number] => 20060110843
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-25
[patent_title] => 'Method of manufacturing an external force detection sensor'
[patent_app_type] => utility
[patent_app_number] => 11/296052
[patent_app_country] => US
[patent_app_date] => 2005-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7889
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0110/20060110843.pdf
[firstpage_image] =>[orig_patent_app_number] => 11296052
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/296052 | Method of manufacturing external force detection sensor | Dec 5, 2005 | Issued |
Array
(
[id] => 390252
[patent_doc_number] => 07300848
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-27
[patent_title] => 'Semiconductor device having a recess gate for improved reliability'
[patent_app_type] => utility
[patent_app_number] => 11/287594
[patent_app_country] => US
[patent_app_date] => 2005-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 4590
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 293
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/300/07300848.pdf
[firstpage_image] =>[orig_patent_app_number] => 11287594
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/287594 | Semiconductor device having a recess gate for improved reliability | Nov 27, 2005 | Issued |
Array
(
[id] => 5095768
[patent_doc_number] => 20070117377
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-24
[patent_title] => 'Conductor-dielectric structure and method for fabricating'
[patent_app_type] => utility
[patent_app_number] => 11/286093
[patent_app_country] => US
[patent_app_date] => 2005-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2412
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0117/20070117377.pdf
[firstpage_image] =>[orig_patent_app_number] => 11286093
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/286093 | Conductor-dielectric structure and method for fabricating | Nov 22, 2005 | Abandoned |
Array
(
[id] => 4604697
[patent_doc_number] => 07985677
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-26
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/283964
[patent_app_country] => US
[patent_app_date] => 2005-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 78
[patent_no_of_words] => 34686
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/985/07985677.pdf
[firstpage_image] =>[orig_patent_app_number] => 11283964
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/283964 | Method of manufacturing semiconductor device | Nov 21, 2005 | Issued |
Array
(
[id] => 5613982
[patent_doc_number] => 20060115910
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-01
[patent_title] => 'Method for predicting lifetime of insulating film'
[patent_app_type] => utility
[patent_app_number] => 11/283993
[patent_app_country] => US
[patent_app_date] => 2005-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9323
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0115/20060115910.pdf
[firstpage_image] =>[orig_patent_app_number] => 11283993
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/283993 | Method for predicting lifetime of insulating film | Nov 21, 2005 | Abandoned |
Array
(
[id] => 220957
[patent_doc_number] => 07608503
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-10-27
[patent_title] => 'Side wall active pin memory and manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 11/285473
[patent_app_country] => US
[patent_app_date] => 2005-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 24
[patent_no_of_words] => 7205
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/608/07608503.pdf
[firstpage_image] =>[orig_patent_app_number] => 11285473
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/285473 | Side wall active pin memory and manufacturing method | Nov 20, 2005 | Issued |
Array
(
[id] => 5747989
[patent_doc_number] => 20060110921
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-25
[patent_title] => 'Methods for forming a structured tungsten layer and forming a semiconductor device using the same'
[patent_app_type] => utility
[patent_app_number] => 11/282594
[patent_app_country] => US
[patent_app_date] => 2005-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3373
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0110/20060110921.pdf
[firstpage_image] =>[orig_patent_app_number] => 11282594
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/282594 | Methods for forming a structured tungsten layer and forming a semiconductor device using the same | Nov 20, 2005 | Issued |