Search

Robert G. Santos

Examiner (ID: 11440, Phone: (571)272-7048 , Office: P/3673 )

Most Active Art Unit
3673
Art Unit(s)
3633, 3628, 3673, 3508
Total Applications
2492
Issued Applications
1855
Pending Applications
190
Abandoned Applications
474

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 559656 [patent_doc_number] => 07161205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Semiconductor memory device with cylindrical storage electrode and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/992963 [patent_app_country] => US [patent_app_date] => 2004-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3473 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/161/07161205.pdf [firstpage_image] =>[orig_patent_app_number] => 10992963 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/992963
Semiconductor memory device with cylindrical storage electrode and method of manufacturing the same Nov 17, 2004 Issued
Array ( [id] => 489613 [patent_doc_number] => 07214629 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-08 [patent_title] => 'Strain-silicon CMOS with dual-stressed film' [patent_app_type] => utility [patent_app_number] => 10/989673 [patent_app_country] => US [patent_app_date] => 2004-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3622 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/214/07214629.pdf [firstpage_image] =>[orig_patent_app_number] => 10989673 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/989673
Strain-silicon CMOS with dual-stressed film Nov 15, 2004 Issued
Array ( [id] => 609469 [patent_doc_number] => 07151028 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-19 [patent_title] => 'Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability' [patent_app_type] => utility [patent_app_number] => 10/981174 [patent_app_country] => US [patent_app_date] => 2004-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/151/07151028.pdf [firstpage_image] =>[orig_patent_app_number] => 10981174 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/981174
Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability Nov 3, 2004 Issued
Array ( [id] => 4557721 [patent_doc_number] => 07838358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Semiconductor device with capacitor and fuse and its manufacture method' [patent_app_type] => utility [patent_app_number] => 10/971674 [patent_app_country] => US [patent_app_date] => 2004-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 67 [patent_no_of_words] => 29721 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/838/07838358.pdf [firstpage_image] =>[orig_patent_app_number] => 10971674 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/971674
Semiconductor device with capacitor and fuse and its manufacture method Oct 24, 2004 Issued
Array ( [id] => 449744 [patent_doc_number] => 07250646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-31 [patent_title] => 'TFT mask ROM and method for making same' [patent_app_type] => utility [patent_app_number] => 10/965780 [patent_app_country] => US [patent_app_date] => 2004-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7879 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/250/07250646.pdf [firstpage_image] =>[orig_patent_app_number] => 10965780 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/965780
TFT mask ROM and method for making same Oct 17, 2004 Issued
Array ( [id] => 557029 [patent_doc_number] => 07157325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Method for fabricating semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/959984 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 59 [patent_no_of_words] => 8299 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/157/07157325.pdf [firstpage_image] =>[orig_patent_app_number] => 10959984 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/959984
Method for fabricating semiconductor memory device Oct 7, 2004 Issued
Array ( [id] => 112374 [patent_doc_number] => 07713839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Diamond substrate formation for electronic assemblies' [patent_app_type] => utility [patent_app_number] => 10/960303 [patent_app_country] => US [patent_app_date] => 2004-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/713/07713839.pdf [firstpage_image] =>[orig_patent_app_number] => 10960303 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/960303
Diamond substrate formation for electronic assemblies Oct 5, 2004 Issued
Array ( [id] => 849479 [patent_doc_number] => 07381998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-03 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/949569 [patent_app_country] => US [patent_app_date] => 2004-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5791 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/381/07381998.pdf [firstpage_image] =>[orig_patent_app_number] => 10949569 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/949569
Semiconductor integrated circuit device Sep 23, 2004 Issued
Array ( [id] => 634077 [patent_doc_number] => 07129133 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-31 [patent_title] => 'Method and structure of memory element plug with conductive Ta removed from sidewall at region of memory element film' [patent_app_type] => utility [patent_app_number] => 10/939773 [patent_app_country] => US [patent_app_date] => 2004-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6217 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/129/07129133.pdf [firstpage_image] =>[orig_patent_app_number] => 10939773 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/939773
Method and structure of memory element plug with conductive Ta removed from sidewall at region of memory element film Sep 12, 2004 Issued
Array ( [id] => 6915472 [patent_doc_number] => 20050093033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Field effect transistor and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/933333 [patent_app_country] => US [patent_app_date] => 2004-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10176 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093033.pdf [firstpage_image] =>[orig_patent_app_number] => 10933333 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/933333
Field effect transistor and manufacturing method thereof Sep 2, 2004 Issued
Array ( [id] => 253048 [patent_doc_number] => 07579683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-25 [patent_title] => 'Memory interface optimized for stacked configurations' [patent_app_type] => utility [patent_app_number] => 10/934113 [patent_app_country] => US [patent_app_date] => 2004-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 20335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/579/07579683.pdf [firstpage_image] =>[orig_patent_app_number] => 10934113 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/934113
Memory interface optimized for stacked configurations Sep 2, 2004 Issued
Array ( [id] => 5685903 [patent_doc_number] => 20060284218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Nanoelectonic devices based on nanowire networks' [patent_app_type] => utility [patent_app_number] => 10/570277 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8444 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20060284218.pdf [firstpage_image] =>[orig_patent_app_number] => 10570277 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/570277
Nanoelectonic devices based on nanowire networks Aug 31, 2004 Abandoned
Array ( [id] => 982337 [patent_doc_number] => 06927181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Transfer robot and inspection method for thin substrate' [patent_app_type] => utility [patent_app_number] => 10/930952 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2840 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927181.pdf [firstpage_image] =>[orig_patent_app_number] => 10930952 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/930952
Transfer robot and inspection method for thin substrate Aug 31, 2004 Issued
Array ( [id] => 759399 [patent_doc_number] => 07011717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-14 [patent_title] => 'Method for heat treatment of silicon wafers and silicon wafer' [patent_app_type] => utility [patent_app_number] => 10/929480 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8940 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/011/07011717.pdf [firstpage_image] =>[orig_patent_app_number] => 10929480 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929480
Method for heat treatment of silicon wafers and silicon wafer Aug 30, 2004 Issued
Array ( [id] => 7127436 [patent_doc_number] => 20050059180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Masked spacer etching for imagers' [patent_app_type] => utility [patent_app_number] => 10/921274 [patent_app_country] => US [patent_app_date] => 2004-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4952 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20050059180.pdf [firstpage_image] =>[orig_patent_app_number] => 10921274 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/921274
Masked spacer etching for imagers Aug 18, 2004 Issued
Array ( [id] => 5591059 [patent_doc_number] => 20060040511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => '[METHOD OF FABRICATING SHALLOW TRENCH ISOLATION STRUCTURE FOR REDUCING WAFER SCRATCH]' [patent_app_type] => utility [patent_app_number] => 10/711003 [patent_app_country] => US [patent_app_date] => 2004-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2214 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20060040511.pdf [firstpage_image] =>[orig_patent_app_number] => 10711003 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/711003
[METHOD OF FABRICATING SHALLOW TRENCH ISOLATION STRUCTURE FOR REDUCING WAFER SCRATCH] Aug 16, 2004 Abandoned
Array ( [id] => 5066570 [patent_doc_number] => 20070187671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Organic electronic component with high resolution structuring, and method of the production thereof' [patent_app_type] => utility [patent_app_number] => 10/569763 [patent_app_country] => US [patent_app_date] => 2004-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2156 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20070187671.pdf [firstpage_image] =>[orig_patent_app_number] => 10569763 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/569763
Organic electronic component with high resolution structuring, and method of the production thereof Aug 13, 2004 Issued
Array ( [id] => 982326 [patent_doc_number] => 06927170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Methods for making semiconductor device structures with capacitor containers and contact apertures having increased aspect ratios' [patent_app_type] => utility [patent_app_number] => 10/916888 [patent_app_country] => US [patent_app_date] => 2004-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 40 [patent_no_of_words] => 10758 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927170.pdf [firstpage_image] =>[orig_patent_app_number] => 10916888 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/916888
Methods for making semiconductor device structures with capacitor containers and contact apertures having increased aspect ratios Aug 10, 2004 Issued
Array ( [id] => 843512 [patent_doc_number] => 07387944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-17 [patent_title] => 'Method for low temperature bonding and bonded structure' [patent_app_type] => utility [patent_app_number] => 10/913441 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 8297 [patent_no_of_claims] => 96 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/387/07387944.pdf [firstpage_image] =>[orig_patent_app_number] => 10913441 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/913441
Method for low temperature bonding and bonded structure Aug 8, 2004 Issued
Array ( [id] => 630749 [patent_doc_number] => 07132710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Capacitor, semiconductor device having the same, and method of manufacturing the semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/902824 [patent_app_country] => US [patent_app_date] => 2004-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 4272 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/132/07132710.pdf [firstpage_image] =>[orig_patent_app_number] => 10902824 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/902824
Capacitor, semiconductor device having the same, and method of manufacturing the semiconductor device Aug 1, 2004 Issued
Menu