Search

Robert M. Kunemund

Examiner (ID: 16568, Phone: (571)272-1464 , Office: P/1714 )

Most Active Art Unit
1714
Art Unit(s)
1107, 1765, 1103, 1109, 1714, 1722, 1792, 1763
Total Applications
3556
Issued Applications
2781
Pending Applications
191
Abandoned Applications
615

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1011307 [patent_doc_number] => 06901456 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-31 [patent_title] => 'Method and system for SCSI host bus interconnection' [patent_app_type] => utility [patent_app_number] => 09/336649 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2473 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/901/06901456.pdf [firstpage_image] =>[orig_patent_app_number] => 09336649 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/336649
Method and system for SCSI host bus interconnection Jun 17, 1999 Issued
Array ( [id] => 1240796 [patent_doc_number] => 06691183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Second transfer logic causing a first transfer logic to check a data ready bit prior to each of multibit transfer of a continous transfer operation' [patent_app_type] => B1 [patent_app_number] => 09/314487 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7502 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691183.pdf [firstpage_image] =>[orig_patent_app_number] => 09314487 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314487
Second transfer logic causing a first transfer logic to check a data ready bit prior to each of multibit transfer of a continous transfer operation May 17, 1999 Issued
Array ( [id] => 7644160 [patent_doc_number] => 06473814 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'System for optimally tuning a burst length by setting a maximum burst length based on a latency timer value and adjusting the maximum burst length based on a cache line size' [patent_app_type] => B1 [patent_app_number] => 09/303635 [patent_app_country] => US [patent_app_date] => 1999-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473814.pdf [firstpage_image] =>[orig_patent_app_number] => 09303635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/303635
System for optimally tuning a burst length by setting a maximum burst length based on a latency timer value and adjusting the maximum burst length based on a cache line size May 2, 1999 Issued
Array ( [id] => 1587554 [patent_doc_number] => 06425089 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Method for generating a clock signal for universal asynchronous receiver transmitter by utilizing a PCI-standardized clock signal' [patent_app_type] => B1 [patent_app_number] => 09/299718 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2718 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425089.pdf [firstpage_image] =>[orig_patent_app_number] => 09299718 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/299718
Method for generating a clock signal for universal asynchronous receiver transmitter by utilizing a PCI-standardized clock signal Apr 25, 1999 Issued
Array ( [id] => 4298195 [patent_doc_number] => 06282588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Data transfer method and device' [patent_app_type] => 1 [patent_app_number] => 9/214084 [patent_app_country] => US [patent_app_date] => 1999-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7469 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282588.pdf [firstpage_image] =>[orig_patent_app_number] => 214084 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/214084
Data transfer method and device Apr 18, 1999 Issued
Array ( [id] => 7631586 [patent_doc_number] => 06665751 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Streaming media player varying a play speed from an original to a maximum allowable slowdown proportionally in accordance with a buffer state' [patent_app_type] => B1 [patent_app_number] => 09/293644 [patent_app_country] => US [patent_app_date] => 1999-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2899 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665751.pdf [firstpage_image] =>[orig_patent_app_number] => 09293644 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293644
Streaming media player varying a play speed from an original to a maximum allowable slowdown proportionally in accordance with a buffer state Apr 16, 1999 Issued
Array ( [id] => 1567196 [patent_doc_number] => 06438626 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'System implementing a state transition having an interface storing a new next state of a self block and exchanging the state information with other block' [patent_app_type] => B1 [patent_app_number] => 09/280545 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4095 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438626.pdf [firstpage_image] =>[orig_patent_app_number] => 09280545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/280545
System implementing a state transition having an interface storing a new next state of a self block and exchanging the state information with other block Mar 29, 1999 Issued
Array ( [id] => 4299313 [patent_doc_number] => 06282659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Feature to facilitate numeric passcode entry' [patent_app_type] => 1 [patent_app_number] => 9/275106 [patent_app_country] => US [patent_app_date] => 1999-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2308 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282659.pdf [firstpage_image] =>[orig_patent_app_number] => 275106 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/275106
Feature to facilitate numeric passcode entry Mar 23, 1999 Issued
Array ( [id] => 1505890 [patent_doc_number] => 06487611 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Seamless distributed job control between a multifunction peripheral and a host' [patent_app_type] => B1 [patent_app_number] => 09/253612 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3343 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487611.pdf [firstpage_image] =>[orig_patent_app_number] => 09253612 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/253612
Seamless distributed job control between a multifunction peripheral and a host Feb 18, 1999 Issued
Array ( [id] => 4346022 [patent_doc_number] => 06330624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Access limiting to only a planar by storing a device public key only within the planar and a planar public key only within the device' [patent_app_type] => 1 [patent_app_number] => 9/246383 [patent_app_country] => US [patent_app_date] => 1999-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3152 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330624.pdf [firstpage_image] =>[orig_patent_app_number] => 246383 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/246383
Access limiting to only a planar by storing a device public key only within the planar and a planar public key only within the device Feb 8, 1999 Issued
Array ( [id] => 6483830 [patent_doc_number] => 20020023180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'METHOD OF CONTROLLING SOFTWARE APPLICATIONS SPECIFIC TO A GROUP OF USERS' [patent_app_type] => new [patent_app_number] => 09/246351 [patent_app_country] => US [patent_app_date] => 1999-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6738 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20020023180.pdf [firstpage_image] =>[orig_patent_app_number] => 09246351 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/246351
Method of controlling software applications specific to a group of users Feb 7, 1999 Issued
Array ( [id] => 5890309 [patent_doc_number] => 20020013866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'RETRIEVAL CHANNELS FOR A DATA CONTROLLER' [patent_app_type] => new [patent_app_number] => 09/224259 [patent_app_country] => US [patent_app_date] => 1998-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 20487 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20020013866.pdf [firstpage_image] =>[orig_patent_app_number] => 09224259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224259
One retrieval channel in a data controller having staging registers and a next pointer register and programming a context of a direct memory access block Dec 30, 1998 Issued
Array ( [id] => 7638648 [patent_doc_number] => 06397273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-28 [patent_title] => 'System having an enhanced parity mechanism in a data assembler/disassembler for use in a pipeline of a host-storage system interface to global memory' [patent_app_type] => B2 [patent_app_number] => 09/213139 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 41 [patent_no_of_words] => 29133 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397273.pdf [firstpage_image] =>[orig_patent_app_number] => 09213139 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/213139
System having an enhanced parity mechanism in a data assembler/disassembler for use in a pipeline of a host-storage system interface to global memory Dec 17, 1998 Issued
Array ( [id] => 950012 [patent_doc_number] => 06963937 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-08 [patent_title] => 'Method and apparatus for providing configurability and customization of adaptive user-input filtration' [patent_app_type] => utility [patent_app_number] => 09/213660 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 8390 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/963/06963937.pdf [firstpage_image] =>[orig_patent_app_number] => 09213660 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/213660
Method and apparatus for providing configurability and customization of adaptive user-input filtration Dec 16, 1998 Issued
Array ( [id] => 4423235 [patent_doc_number] => 06311240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Hardware assisted formatted data transfer system having a source storage controller and a formatting storage controller receiving on-media structure definition and a data definition' [patent_app_type] => 1 [patent_app_number] => 9/213760 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5224 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311240.pdf [firstpage_image] =>[orig_patent_app_number] => 213760 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/213760
Hardware assisted formatted data transfer system having a source storage controller and a formatting storage controller receiving on-media structure definition and a data definition Dec 16, 1998 Issued
Array ( [id] => 4299044 [patent_doc_number] => 06282642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'System for presetting a first or second remote boot protocol by a computer remotely receiving and storing a boot parameter prior to being powered on' [patent_app_type] => 1 [patent_app_number] => 9/195466 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5171 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282642.pdf [firstpage_image] =>[orig_patent_app_number] => 195466 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195466
System for presetting a first or second remote boot protocol by a computer remotely receiving and storing a boot parameter prior to being powered on Nov 17, 1998 Issued
Array ( [id] => 4269800 [patent_doc_number] => 06223233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Wallet for personal information device' [patent_app_type] => 1 [patent_app_number] => 9/189572 [patent_app_country] => US [patent_app_date] => 1998-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 9439 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223233.pdf [firstpage_image] =>[orig_patent_app_number] => 189572 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/189572
Wallet for personal information device Nov 10, 1998 Issued
Array ( [id] => 6283116 [patent_doc_number] => 20020108003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'COMMAND QUEUEING ENGINE' [patent_app_type] => new [patent_app_number] => 09/183694 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 20413 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20020108003.pdf [firstpage_image] =>[orig_patent_app_number] => 09183694 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183694
Command queueing engine Oct 29, 1998 Issued
Array ( [id] => 4373740 [patent_doc_number] => 06292852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'High-performance multiple-media duplicating system' [patent_app_type] => 1 [patent_app_number] => 9/178072 [patent_app_country] => US [patent_app_date] => 1998-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6951 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 472 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292852.pdf [firstpage_image] =>[orig_patent_app_number] => 178072 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/178072
High-performance multiple-media duplicating system Oct 22, 1998 Issued
Array ( [id] => 4325052 [patent_doc_number] => 06253263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'System with logic gates having a progressive number of inputs connected to a first connection matrix receiving signals to be arbitrated from peripheral devices' [patent_app_type] => 1 [patent_app_number] => 9/176534 [patent_app_country] => US [patent_app_date] => 1998-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2590 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253263.pdf [firstpage_image] =>[orig_patent_app_number] => 176534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/176534
System with logic gates having a progressive number of inputs connected to a first connection matrix receiving signals to be arbitrated from peripheral devices Oct 20, 1998 Issued
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