Robert M. Kunemund

Array ( [id] => 4291894 [patent_doc_number] => 06247077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Highly-scalable parallel processing computer system architecture' [patent_app_type] => 1 [patent_app_number] => 9/020198 [patent_app_country] => US [patent_app_date] => 1998-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 23717 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247077.pdf [firstpage_image] =>[orig_patent_app_number] => 020198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152154 [patent_doc_number] => 06148349 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Dynamic and consistent naming of fabric attached storage by a file system on a compute node storing information mapping API system I/O calls for data objects with a globally unique identification' [patent_app_type] => 1 [patent_app_number] => 9/019933 [patent_app_country] => US [patent_app_date] => 1998-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 24135 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148349.pdf [firstpage_image] =>[orig_patent_app_number] => 019933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4123684 [patent_doc_number] => 06101561 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'System for providing an increase in digital data transmission rate over a parallel bus by converting binary format voltages to encoded analog format currents' [patent_app_type] => 1 [patent_app_number] => 9/019592 [patent_app_country] => US [patent_app_date] => 1998-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101561.pdf [firstpage_image] =>[orig_patent_app_number] => 019592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4203387 [patent_doc_number] => 06161151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Object-oriented global resource conflict resolver formatting resource requirements into a predetermined standard format and iteratively computing a resource assignment for each I/O function' [patent_app_type] => 1 [patent_app_number] => 9/016681 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 31346 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/161/06161151.pdf [firstpage_image] =>[orig_patent_app_number] => 016681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4103463 [patent_doc_number] => 06026451 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'System for controlling a dispatch of requested data packets by generating size signals for buffer space availability and preventing a dispatch prior to a data request granted signal asserted' [patent_app_type] => 1 [patent_app_number] => 8/996303 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6882 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026451.pdf [firstpage_image] =>[orig_patent_app_number] => 996303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1443872 [patent_doc_number] => 06336155 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'System for controlling power to stop outputting data from a first port after detecting a connection of an external device to a second port' [patent_app_type] => B1 [patent_app_number] => 08/995897 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7218 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/336/06336155.pdf [firstpage_image] =>[orig_patent_app_number] => 08995897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4084986 [patent_doc_number] => 06009483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'System for dynamically setting and modifying internal functions externally of a data processing apparatus by storing and restoring a state in progress of internal functions being executed' [patent_app_type] => 1 [patent_app_number] => 8/995154 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 47 [patent_no_of_words] => 9142 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009483.pdf [firstpage_image] =>[orig_patent_app_number] => 995154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4176770 [patent_doc_number] => 06105079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Apparatus and method in a network interface device for selectively supplying long bit information related to a data frame to a buffer memory and a read controller for initiation of data transfers' [patent_app_type] => 1 [patent_app_number] => 8/993058 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105079.pdf [firstpage_image] =>[orig_patent_app_number] => 993058 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4225481 [patent_doc_number] => 06029210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Memory initialization system selectively outputting a data between a normal data stored in the memory and a fixed value according to a registered access state' [patent_app_type] => 1 [patent_app_number] => 8/991339 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 16321 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029210.pdf [firstpage_image] =>[orig_patent_app_number] => 991339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3970516 [patent_doc_number] => 05999977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'System for terminating multicast channel and data broadcast when at least two second endpoints do not transmit positive acknowledgment message to first endpont' [patent_app_type] => 1 [patent_app_number] => 8/987332 [patent_app_country] => US [patent_app_date] => 1997-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 42 [patent_no_of_words] => 12120 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999977.pdf [firstpage_image] =>[orig_patent_app_number] => 987332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4121799 [patent_doc_number] => 06052749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'System for forming an intelligent I/O (I.sub.2 O)-aware device by connecting both a peripheral control connector having an I/O processor mounted and non-I.sub.2 O device to same bus' [patent_app_type] => 1 [patent_app_number] => 8/970367 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3731 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052749.pdf [firstpage_image] =>[orig_patent_app_number] => 970367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4210880 [patent_doc_number] => 06044412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Integrated circuit pin sharing method and apparatus for diverse memory devices by multiplexing subsets of pins in accordance with operation modes' [patent_app_type] => 1 [patent_app_number] => 8/955261 [patent_app_country] => US [patent_app_date] => 1997-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2197 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044412.pdf [firstpage_image] =>[orig_patent_app_number] => 955261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4225455 [patent_doc_number] => 06029208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'System for generating block address by replacing second count with second valid block address whenever sync is detected or symbol count is reached in one complete block' [patent_app_type] => 1 [patent_app_number] => 8/947848 [patent_app_country] => US [patent_app_date] => 1997-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 6004 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029208.pdf [firstpage_image] =>[orig_patent_app_number] => 947848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4304499 [patent_doc_number] => 06269412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Apparatus for recording information system events' [patent_app_type] => 1 [patent_app_number] => 8/942381 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7143 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269412.pdf [firstpage_image] =>[orig_patent_app_number] => 942381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4021432 [patent_doc_number] => 05987535 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'User interface providing immediate status and capability indicators of an imaging system on a network by displaying channel connections, features in use, availability, and current operations' [patent_app_type] => 1 [patent_app_number] => 8/929519 [patent_app_country] => US [patent_app_date] => 1997-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2715 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987535.pdf [firstpage_image] =>[orig_patent_app_number] => 929519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3969810 [patent_doc_number] => 05958024 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'System having a receive data register for storing at least nine data bits of frame and status bits indicating the status of asynchronous serial receiver' [patent_app_type] => 1 [patent_app_number] => 8/920930 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 7167 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958024.pdf [firstpage_image] =>[orig_patent_app_number] => 920930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1495431 [patent_doc_number] => 06418533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-09 [patent_title] => 'J system for securing a portable computer which optionally requires an entry of an invalid power on password (POP), by forcing an entry of a valid POP' [patent_app_type] => B2 [patent_app_number] => 08/927096 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3413 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418533.pdf [firstpage_image] =>[orig_patent_app_number] => 08927096 [rel_patent_id] =>[rel_patent_doc_number] =>)