Search

Robert R. Raevis

Examiner (ID: 9425, Phone: (571)272-2204 , Office: P/2856 )

Most Active Art Unit
2856
Art Unit(s)
2855, 3621, 2502, 2212, 2856, 2605, 2607, 2861
Total Applications
6011
Issued Applications
4922
Pending Applications
293
Abandoned Applications
846

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2755601 [patent_doc_number] => 05021785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-04 [patent_title] => 'Floating point digital to analog converter with bias to establish range midpoint' [patent_app_type] => 1 [patent_app_number] => 7/463876 [patent_app_country] => US [patent_app_date] => 1990-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4205 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/021/05021785.pdf [firstpage_image] =>[orig_patent_app_number] => 463876 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/463876
Floating point digital to analog converter with bias to establish range midpoint Jan 4, 1990 Issued
Array ( [id] => 2980267 [patent_doc_number] => 05182560 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-26 [patent_title] => 'Analog-to-digital converter for high speed low power applications' [patent_app_type] => 1 [patent_app_number] => 7/455126 [patent_app_country] => US [patent_app_date] => 1989-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4785 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/182/05182560.pdf [firstpage_image] =>[orig_patent_app_number] => 455126 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/455126
Analog-to-digital converter for high speed low power applications Dec 21, 1989 Issued
07/452851 HEAT FLOW DETECTOR FOR RECESSED INCANDESCENT FIXTURES Dec 18, 1989 Abandoned
Array ( [id] => 2749453 [patent_doc_number] => 05028926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-02 [patent_title] => 'Successive type analog-to-digital converter with a variable reference voltage for the digital to analog converter' [patent_app_type] => 1 [patent_app_number] => 7/447074 [patent_app_country] => US [patent_app_date] => 1989-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8604 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/028/05028926.pdf [firstpage_image] =>[orig_patent_app_number] => 447074 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/447074
Successive type analog-to-digital converter with a variable reference voltage for the digital to analog converter Dec 6, 1989 Issued
07/443070 MULTI-LAYER SEMICONDUCTOR DEVICE Nov 29, 1989 Abandoned
Array ( [id] => 2769405 [patent_doc_number] => 04994803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-19 [patent_title] => 'Random number dither circuit for digital-to-analog output signal linearity' [patent_app_type] => 1 [patent_app_number] => 7/442278 [patent_app_country] => US [patent_app_date] => 1989-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1350 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/994/04994803.pdf [firstpage_image] =>[orig_patent_app_number] => 442278 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/442278
Random number dither circuit for digital-to-analog output signal linearity Nov 26, 1989 Issued
Array ( [id] => 2700641 [patent_doc_number] => 04996530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-26 [patent_title] => 'Statistically based continuous autocalibration method and apparatus' [patent_app_type] => 1 [patent_app_number] => 7/442379 [patent_app_country] => US [patent_app_date] => 1989-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 10654 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/996/04996530.pdf [firstpage_image] =>[orig_patent_app_number] => 442379 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/442379
Statistically based continuous autocalibration method and apparatus Nov 26, 1989 Issued
07/441681 PARALLEL PROCESSORS SEQEUNTIALLY ENCODING/DECODING COMPACTION MAINTAINING FORMAT COMPATIBILITY Nov 21, 1989 Abandoned
Array ( [id] => 2637927 [patent_doc_number] => 04937576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-26 [patent_title] => 'Dither circuit responsive to zero input signal level' [patent_app_type] => 1 [patent_app_number] => 7/440175 [patent_app_country] => US [patent_app_date] => 1989-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3837 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/937/04937576.pdf [firstpage_image] =>[orig_patent_app_number] => 440175 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/440175
Dither circuit responsive to zero input signal level Nov 21, 1989 Issued
Array ( [id] => 2884433 [patent_doc_number] => 05119092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-02 [patent_title] => 'Apparatus for encoding, decoding, and storing waveforms' [patent_app_type] => 1 [patent_app_number] => 7/438869 [patent_app_country] => US [patent_app_date] => 1989-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 10234 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/119/05119092.pdf [firstpage_image] =>[orig_patent_app_number] => 438869 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/438869
Apparatus for encoding, decoding, and storing waveforms Nov 19, 1989 Issued
Array ( [id] => 2842911 [patent_doc_number] => 05121118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'Method and apparatus for achieving controlled supplemental signal processing during analog-to-digital signal conversion' [patent_app_type] => 1 [patent_app_number] => 7/435418 [patent_app_country] => US [patent_app_date] => 1989-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5921 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/121/05121118.pdf [firstpage_image] =>[orig_patent_app_number] => 435418 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/435418
Method and apparatus for achieving controlled supplemental signal processing during analog-to-digital signal conversion Nov 12, 1989 Issued
Array ( [id] => 2839111 [patent_doc_number] => 05099381 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-24 [patent_title] => 'Enable circuit with embedded thermal turn-off' [patent_app_type] => 1 [patent_app_number] => 7/433555 [patent_app_country] => US [patent_app_date] => 1989-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2011 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/099/05099381.pdf [firstpage_image] =>[orig_patent_app_number] => 433555 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/433555
Enable circuit with embedded thermal turn-off Nov 7, 1989 Issued
Array ( [id] => 2714502 [patent_doc_number] => 05061928 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-29 [patent_title] => 'System and method of scaling error signals of caseload second order modulators' [patent_app_type] => 1 [patent_app_number] => 7/430265 [patent_app_country] => US [patent_app_date] => 1989-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2800 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/061/05061928.pdf [firstpage_image] =>[orig_patent_app_number] => 430265 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/430265
System and method of scaling error signals of caseload second order modulators Nov 1, 1989 Issued
Array ( [id] => 2674982 [patent_doc_number] => 04999626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-12 [patent_title] => 'Apparatus having a modular decimation architecture' [patent_app_type] => 1 [patent_app_number] => 7/428628 [patent_app_country] => US [patent_app_date] => 1989-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3827 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/999/04999626.pdf [firstpage_image] =>[orig_patent_app_number] => 428628 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/428628
Apparatus having a modular decimation architecture Oct 29, 1989 Issued
Array ( [id] => 2769369 [patent_doc_number] => 04994801 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-19 [patent_title] => 'Apparatus adaptable for use in effecting communications between an analog device and a digital device' [patent_app_type] => 1 [patent_app_number] => 7/428614 [patent_app_country] => US [patent_app_date] => 1989-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8072 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/994/04994801.pdf [firstpage_image] =>[orig_patent_app_number] => 428614 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/428614
Apparatus adaptable for use in effecting communications between an analog device and a digital device Oct 29, 1989 Issued
Array ( [id] => 2751274 [patent_doc_number] => 05003309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-26 [patent_title] => 'Apparatus having shared architecture for analog-to-digital and for digital-to-analog signal conversion' [patent_app_type] => 1 [patent_app_number] => 7/428629 [patent_app_country] => US [patent_app_date] => 1989-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2140 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/003/05003309.pdf [firstpage_image] =>[orig_patent_app_number] => 428629 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/428629
Apparatus having shared architecture for analog-to-digital and for digital-to-analog signal conversion Oct 29, 1989 Issued
Array ( [id] => 2676699 [patent_doc_number] => 05073778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-17 [patent_title] => 'Digital to analog converter with dither using two parallel paths' [patent_app_type] => 1 [patent_app_number] => 7/428958 [patent_app_country] => US [patent_app_date] => 1989-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2439 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/073/05073778.pdf [firstpage_image] =>[orig_patent_app_number] => 428958 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/428958
Digital to analog converter with dither using two parallel paths Oct 29, 1989 Issued
Array ( [id] => 2700604 [patent_doc_number] => 04996528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-26 [patent_title] => 'Apparatus having shared modular architecture for decimation and interpolation' [patent_app_type] => 1 [patent_app_number] => 7/434271 [patent_app_country] => US [patent_app_date] => 1989-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7220 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/996/04996528.pdf [firstpage_image] =>[orig_patent_app_number] => 434271 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/434271
Apparatus having shared modular architecture for decimation and interpolation Oct 29, 1989 Issued
Array ( [id] => 2593420 [patent_doc_number] => 04963870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-16 [patent_title] => 'Digital to analog converter with compensation memory addressed by lower order bits' [patent_app_type] => 1 [patent_app_number] => 7/425572 [patent_app_country] => US [patent_app_date] => 1989-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4644 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/963/04963870.pdf [firstpage_image] =>[orig_patent_app_number] => 425572 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/425572
Digital to analog converter with compensation memory addressed by lower order bits Oct 22, 1989 Issued
Array ( [id] => 2751298 [patent_doc_number] => 05003310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-26 [patent_title] => 'Analog data acquisition circuit with digital logic control' [patent_app_type] => 1 [patent_app_number] => 7/414878 [patent_app_country] => US [patent_app_date] => 1989-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2607 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/003/05003310.pdf [firstpage_image] =>[orig_patent_app_number] => 414878 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/414878
Analog data acquisition circuit with digital logic control Sep 28, 1989 Issued
Menu