Search

Robert R. Raevis

Examiner (ID: 9425, Phone: (571)272-2204 , Office: P/2856 )

Most Active Art Unit
2856
Art Unit(s)
2855, 3621, 2502, 2212, 2856, 2605, 2607, 2861
Total Applications
6011
Issued Applications
4922
Pending Applications
293
Abandoned Applications
846

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7244569 [patent_doc_number] => 20050073444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Cylindrical cover-attached encoder apparatus' [patent_app_type] => utility [patent_app_number] => 10/959084 [patent_app_country] => US [patent_app_date] => 2004-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4653 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20050073444.pdf [firstpage_image] =>[orig_patent_app_number] => 10959084 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/959084
Cylindrical cover-attached encoder apparatus Oct 6, 2004 Abandoned
Array ( [id] => 5719066 [patent_doc_number] => 20060071839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Analog-to-digital converter' [patent_app_type] => utility [patent_app_number] => 10/959380 [patent_app_country] => US [patent_app_date] => 2004-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2988 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20060071839.pdf [firstpage_image] =>[orig_patent_app_number] => 10959380 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/959380
Analog-to-digital converter Oct 5, 2004 Abandoned
Array ( [id] => 5719070 [patent_doc_number] => 20060071843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Memory efficient interleaving' [patent_app_type] => utility [patent_app_number] => 10/959281 [patent_app_country] => US [patent_app_date] => 2004-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6297 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20060071843.pdf [firstpage_image] =>[orig_patent_app_number] => 10959281 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/959281
Memory efficient interleaving Oct 4, 2004 Issued
Array ( [id] => 7244623 [patent_doc_number] => 20050073454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'A/D converter, digital PLL circuit using the same, and information recording apparatus using the same' [patent_app_type] => utility [patent_app_number] => 10/957385 [patent_app_country] => US [patent_app_date] => 2004-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4147 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20050073454.pdf [firstpage_image] =>[orig_patent_app_number] => 10957385 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/957385
A/D converter, digital PLL circuit using the same, and information recording apparatus using the same Sep 30, 2004 Issued
Array ( [id] => 722172 [patent_doc_number] => 07049989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Unified analog input front end apparatus and method' [patent_app_type] => utility [patent_app_number] => 10/954485 [patent_app_country] => US [patent_app_date] => 2004-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7042 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/049/07049989.pdf [firstpage_image] =>[orig_patent_app_number] => 10954485 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/954485
Unified analog input front end apparatus and method Sep 30, 2004 Issued
Array ( [id] => 775363 [patent_doc_number] => 07002507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Pipelined and cyclic analog-to-digital converters' [patent_app_type] => utility [patent_app_number] => 10/945880 [patent_app_country] => US [patent_app_date] => 2004-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 17316 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002507.pdf [firstpage_image] =>[orig_patent_app_number] => 10945880 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/945880
Pipelined and cyclic analog-to-digital converters Sep 21, 2004 Issued
Array ( [id] => 5824315 [patent_doc_number] => 20060061493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Apparatus and method for assigning circuit card base addresses using thermometer codes' [patent_app_type] => utility [patent_app_number] => 10/946788 [patent_app_country] => US [patent_app_date] => 2004-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2658 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20060061493.pdf [firstpage_image] =>[orig_patent_app_number] => 10946788 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/946788
Apparatus and method for assigning circuit card base addresses using thermometer codes Sep 21, 2004 Abandoned
Array ( [id] => 753017 [patent_doc_number] => 07023373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Multi-stage ADC with shared amplifier and reference voltage selection' [patent_app_type] => utility [patent_app_number] => 10/945689 [patent_app_country] => US [patent_app_date] => 2004-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 13617 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 381 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023373.pdf [firstpage_image] =>[orig_patent_app_number] => 10945689 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/945689
Multi-stage ADC with shared amplifier and reference voltage selection Sep 20, 2004 Issued
Array ( [id] => 947000 [patent_doc_number] => 06965334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-15 [patent_title] => 'Variable bandgap reference' [patent_app_type] => utility [patent_app_number] => 10/944510 [patent_app_country] => US [patent_app_date] => 2004-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6694 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965334.pdf [firstpage_image] =>[orig_patent_app_number] => 10944510 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/944510
Variable bandgap reference Sep 16, 2004 Issued
Array ( [id] => 5724817 [patent_doc_number] => 20060055577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Minimized differential SAR-type column-wide ADC for CMOS image sensors' [patent_app_type] => utility [patent_app_number] => 10/929578 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13313 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20060055577.pdf [firstpage_image] =>[orig_patent_app_number] => 10929578 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929578
Minimized differential SAR-type column-wide ADC for CMOS image sensors Aug 30, 2004 Issued
Array ( [id] => 7409287 [patent_doc_number] => 20040263362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Coding method and device' [patent_app_type] => new [patent_app_number] => 10/488998 [patent_app_country] => US [patent_app_date] => 2004-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6064 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20040263362.pdf [firstpage_image] =>[orig_patent_app_number] => 10488998 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/488998
Coding method and device Aug 22, 2004 Abandoned
Array ( [id] => 7056915 [patent_doc_number] => 20050278090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Method of detecting abnormality of R/D converter' [patent_app_type] => utility [patent_app_number] => 10/916466 [patent_app_country] => US [patent_app_date] => 2004-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4434 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20050278090.pdf [firstpage_image] =>[orig_patent_app_number] => 10916466 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/916466
Method of detecting abnormality of R/D converter Aug 11, 2004 Issued
Array ( [id] => 5589258 [patent_doc_number] => 20060038709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Delta-sigma modulator with selectable noise transfer function' [patent_app_type] => utility [patent_app_number] => 10/917261 [patent_app_country] => US [patent_app_date] => 2004-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5752 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20060038709.pdf [firstpage_image] =>[orig_patent_app_number] => 10917261 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/917261
Delta-sigma modulator with selectable noise transfer function Aug 11, 2004 Issued
Array ( [id] => 448156 [patent_doc_number] => 07253757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Sigma-delta modulator having a clocked delay line' [patent_app_type] => utility [patent_app_number] => 10/909182 [patent_app_country] => US [patent_app_date] => 2004-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1775 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/253/07253757.pdf [firstpage_image] =>[orig_patent_app_number] => 10909182 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/909182
Sigma-delta modulator having a clocked delay line Jul 29, 2004 Issued
Array ( [id] => 7037332 [patent_doc_number] => 20050156766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Signal processing with look-ahead modulator noise quantization minimization' [patent_app_type] => utility [patent_app_number] => 10/900877 [patent_app_country] => US [patent_app_date] => 2004-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6402 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20050156766.pdf [firstpage_image] =>[orig_patent_app_number] => 10900877 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/900877
Signal processing with look-ahead modulator noise quantization minimization Jul 27, 2004 Issued
Array ( [id] => 7008909 [patent_doc_number] => 20050062625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Arrangement for generating a clock signal for a sigma-delta analog-to-digital converter' [patent_app_type] => utility [patent_app_number] => 10/900027 [patent_app_country] => US [patent_app_date] => 2004-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3019 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20050062625.pdf [firstpage_image] =>[orig_patent_app_number] => 10900027 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/900027
Arrangement for generating a clock signal for a sigma-delta analog-to-digital converter Jul 25, 2004 Issued
Array ( [id] => 5796969 [patent_doc_number] => 20060033646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Method and apparatus for minimizing threshold variation from body charge in silicon-on-insulator circuitry' [patent_app_type] => utility [patent_app_number] => 10/896504 [patent_app_country] => US [patent_app_date] => 2004-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2772 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20060033646.pdf [firstpage_image] =>[orig_patent_app_number] => 10896504 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/896504
Method and apparatus for minimizing threshold variation from body charge in silicon-on-insulator circuitry Jul 21, 2004 Issued
Array ( [id] => 5736641 [patent_doc_number] => 20060007031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'CHARGE-DOMAIN A/D CONVERTER EMPLOYING MULTIPLE PIPELINES FOR IMPROVED PRECISION' [patent_app_type] => utility [patent_app_number] => 10/889281 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3782 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20060007031.pdf [firstpage_image] =>[orig_patent_app_number] => 10889281 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889281
Charge-domain A/D converter employing multiple pipelines for improved precision Jul 11, 2004 Issued
Array ( [id] => 938878 [patent_doc_number] => 06972707 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-06 [patent_title] => 'Sub-ranging pipelined charge-domain analog-to-digital converter with improved resolution and reduced power consumption' [patent_app_type] => utility [patent_app_number] => 10/889282 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4169 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972707.pdf [firstpage_image] =>[orig_patent_app_number] => 10889282 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889282
Sub-ranging pipelined charge-domain analog-to-digital converter with improved resolution and reduced power consumption Jul 11, 2004 Issued
Array ( [id] => 775333 [patent_doc_number] => 07002492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'High rate running digital sum-restricted code' [patent_app_type] => utility [patent_app_number] => 10/885987 [patent_app_country] => US [patent_app_date] => 2004-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 17764 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002492.pdf [firstpage_image] =>[orig_patent_app_number] => 10885987 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/885987
High rate running digital sum-restricted code Jul 6, 2004 Issued
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