Search

Robert R. Raevis

Examiner (ID: 9425, Phone: (571)272-2204 , Office: P/2856 )

Most Active Art Unit
2856
Art Unit(s)
2855, 3621, 2502, 2212, 2856, 2605, 2607, 2861
Total Applications
6011
Issued Applications
4922
Pending Applications
293
Abandoned Applications
846

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 941723 [patent_doc_number] => 06970115 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-29 [patent_title] => 'Cycle slip framing system and method for selectively increasing a frame clock cycle to maintain related bits within the same parallel-output frame of a deserializer' [patent_app_type] => utility [patent_app_number] => 10/876985 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5637 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/970/06970115.pdf [firstpage_image] =>[orig_patent_app_number] => 10876985 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876985
Cycle slip framing system and method for selectively increasing a frame clock cycle to maintain related bits within the same parallel-output frame of a deserializer Jun 24, 2004 Issued
Array ( [id] => 7364997 [patent_doc_number] => 20040217895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'ANALOG-DIGITAL CONVERSION APPARATUS' [patent_app_type] => new [patent_app_number] => 10/710180 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6528 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20040217895.pdf [firstpage_image] =>[orig_patent_app_number] => 10710180 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710180
ANALOG-DIGITAL CONVERSION APPARATUS Jun 23, 2004 Abandoned
Array ( [id] => 959213 [patent_doc_number] => 06954161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Cascade delta-sigma modulator' [patent_app_type] => utility [patent_app_number] => 10/865885 [patent_app_country] => US [patent_app_date] => 2004-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6764 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 414 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954161.pdf [firstpage_image] =>[orig_patent_app_number] => 10865885 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/865885
Cascade delta-sigma modulator Jun 13, 2004 Issued
Array ( [id] => 7087153 [patent_doc_number] => 20050007265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'SIGNAL GENERATION USING DAC HAVING SELECTIVELY SWITCHED REGISTERS STORING OUTPUT VALUES' [patent_app_type] => utility [patent_app_number] => 10/866309 [patent_app_country] => US [patent_app_date] => 2004-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6509 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20050007265.pdf [firstpage_image] =>[orig_patent_app_number] => 10866309 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/866309
Signal generation using DAC having selectively switched registers storing output values Jun 9, 2004 Issued
Array ( [id] => 7364986 [patent_doc_number] => 20040217889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Serial-to-parallel conversion circuit, and semiconductor display device employing the same' [patent_app_type] => new [patent_app_number] => 10/859984 [patent_app_country] => US [patent_app_date] => 2004-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 22534 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20040217889.pdf [firstpage_image] =>[orig_patent_app_number] => 10859984 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/859984
Serial-to-parallel conversion circuit, and semiconductor display device employing the same Jun 3, 2004 Issued
Array ( [id] => 7606877 [patent_doc_number] => 07098839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Flash array digitizer' [patent_app_type] => utility [patent_app_number] => 10/861334 [patent_app_country] => US [patent_app_date] => 2004-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6144 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/098/07098839.pdf [firstpage_image] =>[orig_patent_app_number] => 10861334 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/861334
Flash array digitizer Jun 2, 2004 Issued
Array ( [id] => 1054293 [patent_doc_number] => 06859157 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-22 [patent_title] => 'Programmable precision current controlling apparatus' [patent_app_type] => utility [patent_app_number] => 10/859642 [patent_app_country] => US [patent_app_date] => 2004-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859157.pdf [firstpage_image] =>[orig_patent_app_number] => 10859642 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/859642
Programmable precision current controlling apparatus Jun 1, 2004 Issued
Array ( [id] => 264411 [patent_doc_number] => 07570180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Method for syntactically analyzing a bit stream using a schema and a method of generating a bit stream based thereon' [patent_app_type] => utility [patent_app_number] => 10/853796 [patent_app_country] => US [patent_app_date] => 2004-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7934 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/570/07570180.pdf [firstpage_image] =>[orig_patent_app_number] => 10853796 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/853796
Method for syntactically analyzing a bit stream using a schema and a method of generating a bit stream based thereon May 24, 2004 Issued
Array ( [id] => 454480 [patent_doc_number] => 07248194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Bit-detection arrangement and apparatus for reproducing information' [patent_app_type] => utility [patent_app_number] => 10/558712 [patent_app_country] => US [patent_app_date] => 2004-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 7264 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 410 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/248/07248194.pdf [firstpage_image] =>[orig_patent_app_number] => 10558712 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/558712
Bit-detection arrangement and apparatus for reproducing information May 24, 2004 Issued
Array ( [id] => 7037341 [patent_doc_number] => 20050156775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Adaptive, intelligent transform-based analog to information converter method and system' [patent_app_type] => utility [patent_app_number] => 10/845487 [patent_app_country] => US [patent_app_date] => 2004-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14951 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20050156775.pdf [firstpage_image] =>[orig_patent_app_number] => 10845487 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/845487
Adaptive, intelligent transform-based analog to information converter method and system May 11, 2004 Issued
Array ( [id] => 448150 [patent_doc_number] => 07253754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Data form converter between serial and parallel' [patent_app_type] => utility [patent_app_number] => 10/842388 [patent_app_country] => US [patent_app_date] => 2004-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 10794 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/253/07253754.pdf [firstpage_image] =>[orig_patent_app_number] => 10842388 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/842388
Data form converter between serial and parallel May 9, 2004 Issued
Array ( [id] => 1009980 [patent_doc_number] => 06900745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Method of scalable gray coding' [patent_app_type] => utility [patent_app_number] => 10/842605 [patent_app_country] => US [patent_app_date] => 2004-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7659 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900745.pdf [firstpage_image] =>[orig_patent_app_number] => 10842605 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/842605
Method of scalable gray coding May 9, 2004 Issued
Array ( [id] => 7273631 [patent_doc_number] => 20040233082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Apparatus and method for auto calibration of display device' [patent_app_type] => new [patent_app_number] => 10/841488 [patent_app_country] => US [patent_app_date] => 2004-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3580 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233082.pdf [firstpage_image] =>[orig_patent_app_number] => 10841488 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/841488
Apparatus and method for auto calibration of display device May 9, 2004 Issued
Array ( [id] => 770988 [patent_doc_number] => 07006030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-28 [patent_title] => 'Semiconductor integrated circuit device and audio appliance employing it' [patent_app_type] => utility [patent_app_number] => 10/839181 [patent_app_country] => US [patent_app_date] => 2004-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2521 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/006/07006030.pdf [firstpage_image] =>[orig_patent_app_number] => 10839181 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/839181
Semiconductor integrated circuit device and audio appliance employing it May 5, 2004 Issued
Array ( [id] => 7314936 [patent_doc_number] => 20040222911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Monolithic semiconductor device capable of suppressing mismatches between repetitive cells' [patent_app_type] => new [patent_app_number] => 10/839087 [patent_app_country] => US [patent_app_date] => 2004-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2485 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20040222911.pdf [firstpage_image] =>[orig_patent_app_number] => 10839087 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/839087
Monolithic semiconductor device capable of suppressing mismatches between repetitive cells May 4, 2004 Issued
Array ( [id] => 954305 [patent_doc_number] => 06958720 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-25 [patent_title] => 'Fine string compensation to minimize digital to analog converter differential nonlinearity error' [patent_app_type] => utility [patent_app_number] => 10/830586 [patent_app_country] => US [patent_app_date] => 2004-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4013 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958720.pdf [firstpage_image] =>[orig_patent_app_number] => 10830586 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/830586
Fine string compensation to minimize digital to analog converter differential nonlinearity error Apr 21, 2004 Issued
Array ( [id] => 7200866 [patent_doc_number] => 20050052298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Digital-to-analog converter circuits including independently sized reference current source transistors and methods of operating same' [patent_app_type] => utility [patent_app_number] => 10/823077 [patent_app_country] => US [patent_app_date] => 2004-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8588 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20050052298.pdf [firstpage_image] =>[orig_patent_app_number] => 10823077 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/823077
Digital-to-analog converter circuits including independently sized reference current source transistors and methods of operating same Apr 12, 2004 Issued
Array ( [id] => 6950369 [patent_doc_number] => 20050225463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'High-speed MASH sigma-delta modulator architecture and method of operation thereof' [patent_app_type] => utility [patent_app_number] => 10/821487 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3856 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20050225463.pdf [firstpage_image] =>[orig_patent_app_number] => 10821487 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/821487
High-speed MASH sigma-delta modulator architecture and method of operation thereof Apr 8, 2004 Abandoned
Array ( [id] => 643391 [patent_doc_number] => 07123173 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-17 [patent_title] => 'Method and system for a feed-forward encoder' [patent_app_type] => utility [patent_app_number] => 10/822183 [patent_app_country] => US [patent_app_date] => 2004-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 2882 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/123/07123173.pdf [firstpage_image] =>[orig_patent_app_number] => 10822183 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/822183
Method and system for a feed-forward encoder Apr 7, 2004 Issued
Array ( [id] => 783914 [patent_doc_number] => 06992603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Single-stage and multi-stage low power interconnect architectures' [patent_app_type] => utility [patent_app_number] => 10/813084 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4423 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/992/06992603.pdf [firstpage_image] =>[orig_patent_app_number] => 10813084 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/813084
Single-stage and multi-stage low power interconnect architectures Mar 30, 2004 Issued
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