Search

Robert R. Raevis

Examiner (ID: 9425, Phone: (571)272-2204 , Office: P/2856 )

Most Active Art Unit
2856
Art Unit(s)
2855, 3621, 2502, 2212, 2856, 2605, 2607, 2861
Total Applications
6011
Issued Applications
4922
Pending Applications
293
Abandoned Applications
846

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1028968 [patent_doc_number] => 06882294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Resistive ladder, summing node circuit, and trimming method for a subranging analog to digital converter' [patent_app_type] => utility [patent_app_number] => 10/635826 [patent_app_country] => US [patent_app_date] => 2003-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7835 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/882/06882294.pdf [firstpage_image] =>[orig_patent_app_number] => 10635826 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/635826
Resistive ladder, summing node circuit, and trimming method for a subranging analog to digital converter Aug 5, 2003 Issued
Array ( [id] => 1121958 [patent_doc_number] => 06798366 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-28 [patent_title] => 'Architecture for a faster max* computation' [patent_app_type] => B1 [patent_app_number] => 10/628699 [patent_app_country] => US [patent_app_date] => 2003-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4102 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/798/06798366.pdf [firstpage_image] =>[orig_patent_app_number] => 10628699 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/628699
Architecture for a faster max* computation Jul 27, 2003 Issued
Array ( [id] => 7222741 [patent_doc_number] => 20040155804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Reducing jitter in mixed-signal integrated circuit devices' [patent_app_type] => new [patent_app_number] => 10/626743 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10998 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20040155804.pdf [firstpage_image] =>[orig_patent_app_number] => 10626743 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/626743
Reducing jitter in mixed-signal integrated circuit devices Jul 24, 2003 Issued
Array ( [id] => 7192035 [patent_doc_number] => 20040085234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Integrated digital calibration circuit and digital to analog converter (DAC)' [patent_app_type] => new [patent_app_number] => 10/627500 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5036 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20040085234.pdf [firstpage_image] =>[orig_patent_app_number] => 10627500 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/627500
Integrated digital calibration circuit and digital to analog converter (DAC) Jul 24, 2003 Issued
Array ( [id] => 7023486 [patent_doc_number] => 20050017880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'CONVERTING DIGITAL SIGNALS' [patent_app_type] => utility [patent_app_number] => 10/625693 [patent_app_country] => US [patent_app_date] => 2003-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6451 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 28 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20050017880.pdf [firstpage_image] =>[orig_patent_app_number] => 10625693 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/625693
Converting digital signals Jul 23, 2003 Issued
Array ( [id] => 1074342 [patent_doc_number] => 06839009 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Analog-to-digital converter methods and structures for interleavably processing data signals and calibration signals' [patent_app_type] => utility [patent_app_number] => 10/622989 [patent_app_country] => US [patent_app_date] => 2003-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5916 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839009.pdf [firstpage_image] =>[orig_patent_app_number] => 10622989 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622989
Analog-to-digital converter methods and structures for interleavably processing data signals and calibration signals Jul 17, 2003 Issued
Array ( [id] => 1126054 [patent_doc_number] => 06795006 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-21 [patent_title] => 'Integrator reset mechanism' [patent_app_type] => B1 [patent_app_number] => 10/622991 [patent_app_country] => US [patent_app_date] => 2003-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2941 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/795/06795006.pdf [firstpage_image] =>[orig_patent_app_number] => 10622991 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622991
Integrator reset mechanism Jul 17, 2003 Issued
Array ( [id] => 522377 [patent_doc_number] => 07193542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Digital data compression robust relative to transmission noise' [patent_app_type] => utility [patent_app_number] => 10/521963 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 7810 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/193/07193542.pdf [firstpage_image] =>[orig_patent_app_number] => 10521963 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/521963
Digital data compression robust relative to transmission noise Jul 15, 2003 Issued
Array ( [id] => 638841 [patent_doc_number] => 07126396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-24 [patent_title] => 'System for clock duty cycle stabilization' [patent_app_type] => utility [patent_app_number] => 10/622150 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2912 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126396.pdf [firstpage_image] =>[orig_patent_app_number] => 10622150 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622150
System for clock duty cycle stabilization Jul 15, 2003 Issued
Array ( [id] => 7391096 [patent_doc_number] => 20040083248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Method for generating random number and random number generator' [patent_app_type] => new [patent_app_number] => 10/618683 [patent_app_country] => US [patent_app_date] => 2003-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2169 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20040083248.pdf [firstpage_image] =>[orig_patent_app_number] => 10618683 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/618683
Method for generating random number and random number generator Jul 14, 2003 Abandoned
Array ( [id] => 7358267 [patent_doc_number] => 20040004511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'DAC cell circuit' [patent_app_type] => new [patent_app_number] => 10/609569 [patent_app_country] => US [patent_app_date] => 2003-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2152 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20040004511.pdf [firstpage_image] =>[orig_patent_app_number] => 10609569 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/609569
DAC cell circuit Jun 30, 2003 Issued
Array ( [id] => 436462 [patent_doc_number] => 07262720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-28 [patent_title] => 'Processing circuit and method for variable-length coding and decoding' [patent_app_type] => utility [patent_app_number] => 10/611182 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 11531 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/262/07262720.pdf [firstpage_image] =>[orig_patent_app_number] => 10611182 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/611182
Processing circuit and method for variable-length coding and decoding Jun 29, 2003 Issued
Array ( [id] => 7423277 [patent_doc_number] => 20040001015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Processing analog signals with respect to timing of related rotary parts' [patent_app_type] => new [patent_app_number] => 10/608699 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8013 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20040001015.pdf [firstpage_image] =>[orig_patent_app_number] => 10608699 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608699
Processing analog signals with respect to timing of related rotary parts Jun 26, 2003 Abandoned
Array ( [id] => 1054292 [patent_doc_number] => 06859156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-22 [patent_title] => 'Variable bandgap reference and applications thereof' [patent_app_type] => utility [patent_app_number] => 10/603545 [patent_app_country] => US [patent_app_date] => 2003-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6649 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859156.pdf [firstpage_image] =>[orig_patent_app_number] => 10603545 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/603545
Variable bandgap reference and applications thereof Jun 24, 2003 Issued
Array ( [id] => 905033 [patent_doc_number] => 07336209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Method and device for data transmission' [patent_app_type] => utility [patent_app_number] => 10/519600 [patent_app_country] => US [patent_app_date] => 2003-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2589 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/336/07336209.pdf [firstpage_image] =>[orig_patent_app_number] => 10519600 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/519600
Method and device for data transmission Jun 19, 2003 Issued
Array ( [id] => 1147060 [patent_doc_number] => 06778121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'High linearity digital-to-analog converter' [patent_app_type] => B2 [patent_app_number] => 10/462086 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3981 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/778/06778121.pdf [firstpage_image] =>[orig_patent_app_number] => 10462086 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/462086
High linearity digital-to-analog converter Jun 12, 2003 Issued
Array ( [id] => 1170340 [patent_doc_number] => 06759973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'High resolution position sensor' [patent_app_type] => B2 [patent_app_number] => 10/275664 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4060 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/759/06759973.pdf [firstpage_image] =>[orig_patent_app_number] => 10275664 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/275664
High resolution position sensor May 20, 2003 Issued
Array ( [id] => 982878 [patent_doc_number] => 06927722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Series capacitive component for switched-capacitor circuits consisting of series-connected capacitors' [patent_app_type] => utility [patent_app_number] => 10/441348 [patent_app_country] => US [patent_app_date] => 2003-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4623 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927722.pdf [firstpage_image] =>[orig_patent_app_number] => 10441348 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/441348
Series capacitive component for switched-capacitor circuits consisting of series-connected capacitors May 19, 2003 Issued
Array ( [id] => 973209 [patent_doc_number] => 06937178 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-30 [patent_title] => 'Gradient insensitive split-core digital to analog converter' [patent_app_type] => utility [patent_app_number] => 10/440080 [patent_app_country] => US [patent_app_date] => 2003-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9993 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/937/06937178.pdf [firstpage_image] =>[orig_patent_app_number] => 10440080 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/440080
Gradient insensitive split-core digital to analog converter May 14, 2003 Issued
Array ( [id] => 7141823 [patent_doc_number] => 20050117491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Data recording medium, data recording method and device, and encode method and device' [patent_app_type] => utility [patent_app_number] => 10/483622 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12877 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20050117491.pdf [firstpage_image] =>[orig_patent_app_number] => 10483622 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/483622
Data recording medium, data recording method and device, and encode method and device May 11, 2003 Issued
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