
Robert R. Raevis
Examiner (ID: 9425, Phone: (571)272-2204 , Office: P/2856 )
| Most Active Art Unit | 2856 |
| Art Unit(s) | 2855, 3621, 2502, 2212, 2856, 2605, 2607, 2861 |
| Total Applications | 6011 |
| Issued Applications | 4922 |
| Pending Applications | 293 |
| Abandoned Applications | 846 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1584018
[patent_doc_number] => 06424284
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-23
[patent_title] => 'Baseband receiver including dual port DAC'
[patent_app_type] => B1
[patent_app_number] => 09/653570
[patent_app_country] => US
[patent_app_date] => 2000-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2872
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 243
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/424/06424284.pdf
[firstpage_image] =>[orig_patent_app_number] => 09653570
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/653570 | Baseband receiver including dual port DAC | Aug 30, 2000 | Issued |
Array
(
[id] => 1442410
[patent_doc_number] => 06335697
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-01
[patent_title] => 'Simplified method of binary/thermometric encoding with an improved resolution'
[patent_app_type] => B1
[patent_app_number] => 09/649676
[patent_app_country] => US
[patent_app_date] => 2000-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3110
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/335/06335697.pdf
[firstpage_image] =>[orig_patent_app_number] => 09649676
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/649676 | Simplified method of binary/thermometric encoding with an improved resolution | Aug 27, 2000 | Issued |
Array
(
[id] => 1577192
[patent_doc_number] => 06469652
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-22
[patent_title] => 'Pipelined analog-to-digital converter using zero-crossing capacitor swapping scheme'
[patent_app_type] => B1
[patent_app_number] => 09/645972
[patent_app_country] => US
[patent_app_date] => 2000-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4561
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 299
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/469/06469652.pdf
[firstpage_image] =>[orig_patent_app_number] => 09645972
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/645972 | Pipelined analog-to-digital converter using zero-crossing capacitor swapping scheme | Aug 23, 2000 | Issued |
Array
(
[id] => 1564057
[patent_doc_number] => 06362762
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-26
[patent_title] => 'Multiple mode analog-to-digital converter employing a single quantizer'
[patent_app_type] => B1
[patent_app_number] => 09/645072
[patent_app_country] => US
[patent_app_date] => 2000-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 5260
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/362/06362762.pdf
[firstpage_image] =>[orig_patent_app_number] => 09645072
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/645072 | Multiple mode analog-to-digital converter employing a single quantizer | Aug 22, 2000 | Issued |
Array
(
[id] => 1433654
[patent_doc_number] => 06340944
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-22
[patent_title] => 'Programmable power consumption pipeline analog-to-digital converter with variable resolution'
[patent_app_type] => B1
[patent_app_number] => 09/643385
[patent_app_country] => US
[patent_app_date] => 2000-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2215
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/340/06340944.pdf
[firstpage_image] =>[orig_patent_app_number] => 09643385
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/643385 | Programmable power consumption pipeline analog-to-digital converter with variable resolution | Aug 20, 2000 | Issued |
Array
(
[id] => 1569458
[patent_doc_number] => 06377197
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'DAC gain compensation for temperature and process variations'
[patent_app_type] => B1
[patent_app_number] => 09/638371
[patent_app_country] => US
[patent_app_date] => 2000-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1868
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/377/06377197.pdf
[firstpage_image] =>[orig_patent_app_number] => 09638371
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/638371 | DAC gain compensation for temperature and process variations | Aug 14, 2000 | Issued |
Array
(
[id] => 1551537
[patent_doc_number] => 06346898
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-12
[patent_title] => 'Multilevel analog to digital data converter having dynamic element matching in a reference data path'
[patent_app_type] => B1
[patent_app_number] => 09/633381
[patent_app_country] => US
[patent_app_date] => 2000-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1944
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/346/06346898.pdf
[firstpage_image] =>[orig_patent_app_number] => 09633381
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/633381 | Multilevel analog to digital data converter having dynamic element matching in a reference data path | Aug 6, 2000 | Issued |
Array
(
[id] => 1494567
[patent_doc_number] => RE037912
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2002-11-26
[patent_title] => 'Variable-length encoder and decoder using symbol/code-word re-association of a coding table'
[patent_app_type] => E1
[patent_app_number] => 09/629108
[patent_app_country] => US
[patent_app_date] => 2000-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2798
[patent_no_of_claims] => 66
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/037/RE037912.pdf
[firstpage_image] =>[orig_patent_app_number] => 09629108
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/629108 | Variable-length encoder and decoder using symbol/code-word re-association of a coding table | Jul 27, 2000 | Issued |
Array
(
[id] => 1555150
[patent_doc_number] => 06348882
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-19
[patent_title] => '5-ary receiver utilizing common mode insensitive differential offset comparator'
[patent_app_type] => B1
[patent_app_number] => 09/625084
[patent_app_country] => US
[patent_app_date] => 2000-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 2851
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 19
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/348/06348882.pdf
[firstpage_image] =>[orig_patent_app_number] => 09625084
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/625084 | 5-ary receiver utilizing common mode insensitive differential offset comparator | Jul 24, 2000 | Issued |
Array
(
[id] => 1433650
[patent_doc_number] => 06340940
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-22
[patent_title] => 'Digital to analog conversion circuits and methods utilizing single-bit delta-SIGMA modulators and multiple-bit digital to analog converters'
[patent_app_type] => B1
[patent_app_number] => 09/618370
[patent_app_country] => US
[patent_app_date] => 2000-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2716
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/340/06340940.pdf
[firstpage_image] =>[orig_patent_app_number] => 09618370
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/618370 | Digital to analog conversion circuits and methods utilizing single-bit delta-SIGMA modulators and multiple-bit digital to analog converters | Jul 17, 2000 | Issued |
Array
(
[id] => 1032098
[patent_doc_number] => 06879266
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-04-12
[patent_title] => 'Memory module including scalable embedded parallel data compression and decompression engines'
[patent_app_type] => utility
[patent_app_number] => 09/616480
[patent_app_country] => US
[patent_app_date] => 2000-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 58
[patent_figures_cnt] => 66
[patent_no_of_words] => 47218
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/879/06879266.pdf
[firstpage_image] =>[orig_patent_app_number] => 09616480
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/616480 | Memory module including scalable embedded parallel data compression and decompression engines | Jul 13, 2000 | Issued |
Array
(
[id] => 1554085
[patent_doc_number] => 06400287
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'DATA STRUCTURE FOR CREATING, SCOPING, AND CONVERTING TO UNICODE DATA FROM SINGLE BYTE CHARACTER SETS, DOUBLE BYTE CHARACTER SETS, OR MIXED CHARACTER SETS COMPRISING BOTH SINGLE BYTE AND DOUBLE BYTE CHARACTER SETS'
[patent_app_type] => B1
[patent_app_number] => 09/612866
[patent_app_country] => US
[patent_app_date] => 2000-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 10119
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/400/06400287.pdf
[firstpage_image] =>[orig_patent_app_number] => 09612866
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/612866 | DATA STRUCTURE FOR CREATING, SCOPING, AND CONVERTING TO UNICODE DATA FROM SINGLE BYTE CHARACTER SETS, DOUBLE BYTE CHARACTER SETS, OR MIXED CHARACTER SETS COMPRISING BOTH SINGLE BYTE AND DOUBLE BYTE CHARACTER SETS | Jul 9, 2000 | Issued |
Array
(
[id] => 88725
[patent_doc_number] => RE041371
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2010-06-08
[patent_title] => 'Two stage analog-to-digital conversion with second stage offset correction'
[patent_app_type] => reissue
[patent_app_number] => 10/923562
[patent_app_country] => US
[patent_app_date] => 2000-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 2606
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/041/RE041371.pdf
[firstpage_image] =>[orig_patent_app_number] => 10923562
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/923562 | Two stage analog-to-digital conversion with second stage offset correction | Jul 5, 2000 | Issued |
Array
(
[id] => 1498318
[patent_doc_number] => 06404376
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-11
[patent_title] => 'Capacitor array having reduced voltage coefficient induced non-linearities'
[patent_app_type] => B1
[patent_app_number] => 09/607475
[patent_app_country] => US
[patent_app_date] => 2000-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 5068
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/404/06404376.pdf
[firstpage_image] =>[orig_patent_app_number] => 09607475
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/607475 | Capacitor array having reduced voltage coefficient induced non-linearities | Jun 29, 2000 | Issued |
Array
(
[id] => 1548729
[patent_doc_number] => 06445312
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-03
[patent_title] => 'Method and device for compression by blocks of digital data'
[patent_app_type] => B1
[patent_app_number] => 09/605375
[patent_app_country] => US
[patent_app_date] => 2000-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7676
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/445/06445312.pdf
[firstpage_image] =>[orig_patent_app_number] => 09605375
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/605375 | Method and device for compression by blocks of digital data | Jun 28, 2000 | Issued |
Array
(
[id] => 1423962
[patent_doc_number] => 06509855
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-21
[patent_title] => 'Digital-to-analog cell having reduced power consumption and method therefor'
[patent_app_type] => B1
[patent_app_number] => 09/606366
[patent_app_country] => US
[patent_app_date] => 2000-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3138
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/509/06509855.pdf
[firstpage_image] =>[orig_patent_app_number] => 09606366
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/606366 | Digital-to-analog cell having reduced power consumption and method therefor | Jun 27, 2000 | Issued |
Array
(
[id] => 1577166
[patent_doc_number] => 06469643
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-22
[patent_title] => 'Information processing system'
[patent_app_type] => B1
[patent_app_number] => 09/603577
[patent_app_country] => US
[patent_app_date] => 2000-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 8501
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/469/06469643.pdf
[firstpage_image] =>[orig_patent_app_number] => 09603577
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/603577 | Information processing system | Jun 25, 2000 | Issued |
Array
(
[id] => 1462645
[patent_doc_number] => 06392575
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-21
[patent_title] => 'Parallel analog-to-digital converter having random/pseudo-random conversion sequencing'
[patent_app_type] => B1
[patent_app_number] => 09/598769
[patent_app_country] => US
[patent_app_date] => 2000-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3294
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/392/06392575.pdf
[firstpage_image] =>[orig_patent_app_number] => 09598769
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/598769 | Parallel analog-to-digital converter having random/pseudo-random conversion sequencing | Jun 21, 2000 | Issued |
Array
(
[id] => 1426435
[patent_doc_number] => 06507303
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-14
[patent_title] => 'Direct digital conversion of baseband signals to super-nyquist frequencies'
[patent_app_type] => B1
[patent_app_number] => 09/584459
[patent_app_country] => US
[patent_app_date] => 2000-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3639
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/507/06507303.pdf
[firstpage_image] =>[orig_patent_app_number] => 09584459
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/584459 | Direct digital conversion of baseband signals to super-nyquist frequencies | May 30, 2000 | Issued |
Array
(
[id] => 4258092
[patent_doc_number] => 06222469
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Synchro-to-digital conversion with windowed peak determination'
[patent_app_type] => 1
[patent_app_number] => 9/577024
[patent_app_country] => US
[patent_app_date] => 2000-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 3898
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/222/06222469.pdf
[firstpage_image] =>[orig_patent_app_number] => 577024
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/577024 | Synchro-to-digital conversion with windowed peak determination | May 22, 2000 | Issued |