Robert R. Raevis

Array ( [id] => 4362648 [patent_doc_number] => 06292116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Techniques and circuitry for accurately sampling high frequency data signals input to an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/571766 [patent_app_country] => US [patent_app_date] => 2000-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6380 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292116.pdf [firstpage_image] =>[orig_patent_app_number] => 571766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4340675 [patent_doc_number] => 06313763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Variable length data packet with adjustable length indicator' [patent_app_type] => 1 [patent_app_number] => 9/561428 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1835 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313763.pdf [firstpage_image] =>[orig_patent_app_number] => 561428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1241723 [patent_doc_number] => 06683546 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'Methods for producing highly compressed software products' [patent_app_type] => B1 [patent_app_number] => 09/558086 [patent_app_country] => US [patent_app_date] => 2000-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 46 [patent_no_of_words] => 12244 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/683/06683546.pdf [firstpage_image] =>[orig_patent_app_number] => 09558086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4416108 [patent_doc_number] => 06300886 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Four-to-six code table, modulation using same but no merging bit, their application to optical disc recording or playing systems' [patent_app_type] => 1 [patent_app_number] => 9/551835 [patent_app_country] => US [patent_app_date] => 2000-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6865 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300886.pdf [firstpage_image] =>[orig_patent_app_number] => 551835 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1487725 [patent_doc_number] => 06366231 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Integrate and fold analog-to-digital converter with saturation prevention' [patent_app_type] => B1 [patent_app_number] => 09/546623 [patent_app_country] => US [patent_app_date] => 2000-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7039 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366231.pdf [firstpage_image] =>[orig_patent_app_number] => 09546623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1569451 [patent_doc_number] => 06377195 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Offset compensation in parallel analogue-digital converters' [patent_app_type] => B1 [patent_app_number] => 09/544335 [patent_app_country] => US [patent_app_date] => 2000-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2108 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377195.pdf [firstpage_image] =>[orig_patent_app_number] => 09544335 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4413195 [patent_doc_number] => 06271782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Delta-sigma A/D converter' [patent_app_type] => 1 [patent_app_number] => 9/541221 [patent_app_country] => US [patent_app_date] => 2000-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 14103 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271782.pdf [firstpage_image] =>[orig_patent_app_number] => 541221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4327769 [patent_doc_number] => 06331832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Auto-ranging digital densitometer with lookup table' [patent_app_type] => 1 [patent_app_number] => 9/541923 [patent_app_country] => US [patent_app_date] => 2000-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7455 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331832.pdf [firstpage_image] =>[orig_patent_app_number] => 541923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4362733 [patent_doc_number] => 06292122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Digital-to-analog interface circuit having adjustable time response' [patent_app_type] => 1 [patent_app_number] => 9/517766 [patent_app_country] => US [patent_app_date] => 2000-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8373 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292122.pdf [firstpage_image] =>[orig_patent_app_number] => 517766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4295188 [patent_doc_number] => 06268815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'High performance switched-capacitor filter for oversampling sigma-delta digital to analog converters' [patent_app_type] => 1 [patent_app_number] => 9/517979 [patent_app_country] => US [patent_app_date] => 2000-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3983 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268815.pdf [firstpage_image] =>[orig_patent_app_number] => 517979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1437148 [patent_doc_number] => 06356217 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Enhanced DC offset correction through bandwidth and clock speed selection' [patent_app_type] => B1 [patent_app_number] => 09/515843 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4713 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356217.pdf [firstpage_image] =>[orig_patent_app_number] => 09515843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4321650 [patent_doc_number] => 06317064 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'DC offset correction adaptable to multiple requirements' [patent_app_type] => 1 [patent_app_number] => 9/515834 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317064.pdf [firstpage_image] =>[orig_patent_app_number] => 515834 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1537754 [patent_doc_number] => 06337644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Constant-current generation circuit, digital/analog conversion circuit, and image processor' [patent_app_type] => B1 [patent_app_number] => 09/486053 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5112 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337644.pdf [firstpage_image] =>[orig_patent_app_number] => 09486053 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1598272 [patent_doc_number] => 06384756 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'High-speed waveform digitizer with a phase correcting means and a method therefor' [patent_app_type] => B1 [patent_app_number] => 09/505955 [patent_app_country] => US [patent_app_date] => 2000-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8460 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/384/06384756.pdf [firstpage_image] =>[orig_patent_app_number] => 09505955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1564071 [patent_doc_number] => 06362766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Variable pulse PWM DAC method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/501357 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362766.pdf [firstpage_image] =>[orig_patent_app_number] => 09501357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4354448 [patent_doc_number] => 06285300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Apparatus and method for reducing power and noise through reduced switching recording in logic devices' [patent_app_type] => 1 [patent_app_number] => 9/501044 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 3708 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285300.pdf [firstpage_image] =>[orig_patent_app_number] => 501044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4362759 [patent_doc_number] => 06292124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Delta-sigma D/A converter' [patent_app_type] => 1 [patent_app_number] => 9/498049 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6479 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292124.pdf [firstpage_image] =>[orig_patent_app_number] => 498049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4362800 [patent_doc_number] => 06292127 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Multiple state electronic device' [patent_app_type] => 1 [patent_app_number] => 9/496968 [patent_app_country] => US [patent_app_date] => 2000-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7684 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292127.pdf [firstpage_image] =>[orig_patent_app_number] => 496968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4295074 [patent_doc_number] => 06268807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Priority encoder/read only memory (ROM) combination' [patent_app_type] => 1 [patent_app_number] => 9/495764 [patent_app_country] => US [patent_app_date] => 2000-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268807.pdf [firstpage_image] =>[orig_patent_app_number] => 495764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6998903 [patent_doc_number] => 20010052870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'A PARALLEL LATCH FOR HIGH SPEED COMPARATOR USING TWO MODES OF OPERATION' [patent_app_type] => new [patent_app_number] => 09/494382 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2623 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20010052870.pdf [firstpage_image] =>[orig_patent_app_number] => 09494382 [rel_patent_id] =>[rel_patent_doc_number] =>)