Search

Robert R. Raevis

Examiner (ID: 9425, Phone: (571)272-2204 , Office: P/2856 )

Most Active Art Unit
2856
Art Unit(s)
2855, 3621, 2502, 2212, 2856, 2605, 2607, 2861
Total Applications
6011
Issued Applications
4922
Pending Applications
293
Abandoned Applications
846

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3990112 [patent_doc_number] => 05861826 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Method and apparatus for calibrating integrated circuit analog-to-digital converters' [patent_app_type] => 1 [patent_app_number] => 8/885273 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3392 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/861/05861826.pdf [firstpage_image] =>[orig_patent_app_number] => 885273 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885273
Method and apparatus for calibrating integrated circuit analog-to-digital converters Jun 29, 1997 Issued
Array ( [id] => 4056691 [patent_doc_number] => 05870043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Pla dac circuit employing a test function' [patent_app_type] => 1 [patent_app_number] => 8/883662 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5022 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870043.pdf [firstpage_image] =>[orig_patent_app_number] => 883662 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883662
Pla dac circuit employing a test function Jun 26, 1997 Issued
Array ( [id] => 3921191 [patent_doc_number] => 06002355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Synchronously pumped substrate analog-to-digital converter (ADC) system and methods' [patent_app_type] => 1 [patent_app_number] => 8/883364 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4849 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002355.pdf [firstpage_image] =>[orig_patent_app_number] => 883364 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883364
Synchronously pumped substrate analog-to-digital converter (ADC) system and methods Jun 25, 1997 Issued
Array ( [id] => 4059873 [patent_doc_number] => 05969648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Quaternary signal encoding' [patent_app_type] => 1 [patent_app_number] => 8/882554 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4249 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969648.pdf [firstpage_image] =>[orig_patent_app_number] => 882554 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882554
Quaternary signal encoding Jun 24, 1997 Issued
Array ( [id] => 4001331 [patent_doc_number] => 05892465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Decoding apparatus and decoding method' [patent_app_type] => 1 [patent_app_number] => 8/880457 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3057 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892465.pdf [firstpage_image] =>[orig_patent_app_number] => 880457 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/880457
Decoding apparatus and decoding method Jun 23, 1997 Issued
Array ( [id] => 3797630 [patent_doc_number] => 05841383 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Current mode track and hold circuit' [patent_app_type] => 1 [patent_app_number] => 8/874064 [patent_app_country] => US [patent_app_date] => 1997-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7011 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841383.pdf [firstpage_image] =>[orig_patent_app_number] => 874064 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874064
Current mode track and hold circuit Jun 11, 1997 Issued
Array ( [id] => 3899368 [patent_doc_number] => 05835039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Self-biasing, low voltage, multiplying DAC' [patent_app_type] => 1 [patent_app_number] => 8/873275 [patent_app_country] => US [patent_app_date] => 1997-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 10502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835039.pdf [firstpage_image] =>[orig_patent_app_number] => 873275 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873275
Self-biasing, low voltage, multiplying DAC Jun 10, 1997 Issued
Array ( [id] => 4112334 [patent_doc_number] => 06100823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Single sensor position encoder providing two levels of resolution' [patent_app_type] => 1 [patent_app_number] => 8/873272 [patent_app_country] => US [patent_app_date] => 1997-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 6070 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100823.pdf [firstpage_image] =>[orig_patent_app_number] => 873272 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873272
Single sensor position encoder providing two levels of resolution Jun 10, 1997 Issued
Array ( [id] => 3786271 [patent_doc_number] => 05818378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Cable length estimation circuit using data signal edge rate detection and analog to digital conversion' [patent_app_type] => 1 [patent_app_number] => 8/872272 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4141 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818378.pdf [firstpage_image] =>[orig_patent_app_number] => 872272 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/872272
Cable length estimation circuit using data signal edge rate detection and analog to digital conversion Jun 9, 1997 Issued
90/004664 DATA COMPRESSION WITH PIPELINE PROCESSOR HAVING SEPARATE MEMORIES Jun 8, 1997 Pending
Array ( [id] => 3991847 [patent_doc_number] => 05910783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Pseudo barrel shifting for entropy encoding' [patent_app_type] => 1 [patent_app_number] => 8/867557 [patent_app_country] => US [patent_app_date] => 1997-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2477 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910783.pdf [firstpage_image] =>[orig_patent_app_number] => 867557 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/867557
Pseudo barrel shifting for entropy encoding Jun 1, 1997 Issued
Array ( [id] => 3748306 [patent_doc_number] => 05786780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Variable-length encoder and decoder using symbol/code-word re-association of a coding table' [patent_app_type] => 1 [patent_app_number] => 8/863952 [patent_app_country] => US [patent_app_date] => 1997-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2787 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/786/05786780.pdf [firstpage_image] =>[orig_patent_app_number] => 863952 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/863952
Variable-length encoder and decoder using symbol/code-word re-association of a coding table May 26, 1997 Issued
Array ( [id] => 3899354 [patent_doc_number] => 05835038 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'DC dither circuitry and method for delta-sigma modulator' [patent_app_type] => 1 [patent_app_number] => 8/853170 [patent_app_country] => US [patent_app_date] => 1997-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3174 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835038.pdf [firstpage_image] =>[orig_patent_app_number] => 853170 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/853170
DC dither circuitry and method for delta-sigma modulator May 7, 1997 Issued
Array ( [id] => 3954558 [patent_doc_number] => 05990820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Current-mode pipelined ADC with time-interleaved sampling and mixed reference and residue scaling' [patent_app_type] => 1 [patent_app_number] => 8/848248 [patent_app_country] => US [patent_app_date] => 1997-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2302 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/990/05990820.pdf [firstpage_image] =>[orig_patent_app_number] => 848248 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/848248
Current-mode pipelined ADC with time-interleaved sampling and mixed reference and residue scaling Apr 28, 1997 Issued
Array ( [id] => 4142325 [patent_doc_number] => 06016114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Apparatus and method of fabricating mixed signal interface in GSM wireless application' [patent_app_type] => 1 [patent_app_number] => 8/840946 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4027 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016114.pdf [firstpage_image] =>[orig_patent_app_number] => 840946 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840946
Apparatus and method of fabricating mixed signal interface in GSM wireless application Apr 20, 1997 Issued
Array ( [id] => 3751447 [patent_doc_number] => 05801649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Matched spectral null encoder/decoder' [patent_app_type] => 1 [patent_app_number] => 8/817865 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12365 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801649.pdf [firstpage_image] =>[orig_patent_app_number] => 817865 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/817865
Matched spectral null encoder/decoder Apr 20, 1997 Issued
Array ( [id] => 3958276 [patent_doc_number] => 05977893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method for testing charge redistribution type digital-to-analog and analog-to-digital converters' [patent_app_type] => 1 [patent_app_number] => 8/844170 [patent_app_country] => US [patent_app_date] => 1997-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2811 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977893.pdf [firstpage_image] =>[orig_patent_app_number] => 844170 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/844170
Method for testing charge redistribution type digital-to-analog and analog-to-digital converters Apr 17, 1997 Issued
Array ( [id] => 3899439 [patent_doc_number] => 05835044 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => '1-Bit A/D converting device with reduced noise component' [patent_app_type] => 1 [patent_app_number] => 8/839571 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4167 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835044.pdf [firstpage_image] =>[orig_patent_app_number] => 839571 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839571
1-Bit A/D converting device with reduced noise component Apr 14, 1997 Issued
Array ( [id] => 4005833 [patent_doc_number] => 05923274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Process for transmitting data coded with adjustable error- correction codes' [patent_app_type] => 1 [patent_app_number] => 8/839245 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2672 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923274.pdf [firstpage_image] =>[orig_patent_app_number] => 839245 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839245
Process for transmitting data coded with adjustable error- correction codes Apr 14, 1997 Issued
Array ( [id] => 3976542 [patent_doc_number] => 05886655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Arithmetic coding context model that accelerates adaptation for small amounts of data' [patent_app_type] => 1 [patent_app_number] => 8/833776 [patent_app_country] => US [patent_app_date] => 1997-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3603 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886655.pdf [firstpage_image] =>[orig_patent_app_number] => 833776 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/833776
Arithmetic coding context model that accelerates adaptation for small amounts of data Apr 8, 1997 Issued
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