Search

Robert R. Raevis

Examiner (ID: 9425, Phone: (571)272-2204 , Office: P/2856 )

Most Active Art Unit
2856
Art Unit(s)
2855, 3621, 2502, 2212, 2856, 2605, 2607, 2861
Total Applications
6011
Issued Applications
4922
Pending Applications
293
Abandoned Applications
846

Applications

Application numberTitle of the applicationFiling DateStatus
08/683879 METHOD FOR COMPRESSING AND DECOMPRESSING INTEGER-VECTOR DATA Jul 18, 1996 Abandoned
Array ( [id] => 3849368 [patent_doc_number] => 05708432 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Coherent sampling digitizer system' [patent_app_type] => 1 [patent_app_number] => 8/684466 [patent_app_country] => US [patent_app_date] => 1996-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8485 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708432.pdf [firstpage_image] =>[orig_patent_app_number] => 684466 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/684466
Coherent sampling digitizer system Jul 18, 1996 Issued
Array ( [id] => 3816134 [patent_doc_number] => 05831562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Differential sample and hold circuit with common mode sampling for an analog-to-digital converter' [patent_app_type] => 1 [patent_app_number] => 8/678976 [patent_app_country] => US [patent_app_date] => 1996-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8767 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831562.pdf [firstpage_image] =>[orig_patent_app_number] => 678976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/678976
Differential sample and hold circuit with common mode sampling for an analog-to-digital converter Jul 11, 1996 Issued
Array ( [id] => 3743661 [patent_doc_number] => 05699061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Method and apparatus for generating NRZI code with limited runs of ones' [patent_app_type] => 1 [patent_app_number] => 8/674285 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 9952 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699061.pdf [firstpage_image] =>[orig_patent_app_number] => 674285 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/674285
Method and apparatus for generating NRZI code with limited runs of ones Jun 30, 1996 Issued
Array ( [id] => 3805154 [patent_doc_number] => 05828328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'High speed dynamic range extension employing a synchronous digital detector' [patent_app_type] => 1 [patent_app_number] => 8/671668 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1729 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828328.pdf [firstpage_image] =>[orig_patent_app_number] => 671668 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/671668
High speed dynamic range extension employing a synchronous digital detector Jun 27, 1996 Issued
Array ( [id] => 4069940 [patent_doc_number] => 05896099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Audio decoder with buffer fullness control' [patent_app_type] => 1 [patent_app_number] => 8/682866 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11418 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896099.pdf [firstpage_image] =>[orig_patent_app_number] => 682866 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/682866
Audio decoder with buffer fullness control Jun 27, 1996 Issued
Array ( [id] => 3840293 [patent_doc_number] => 05815098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Circuit and method for efficiently expanding compressed data stored in memory' [patent_app_type] => 1 [patent_app_number] => 8/647962 [patent_app_country] => US [patent_app_date] => 1996-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10520 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815098.pdf [firstpage_image] =>[orig_patent_app_number] => 647962 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/647962
Circuit and method for efficiently expanding compressed data stored in memory Jun 19, 1996 Issued
Array ( [id] => 3786072 [patent_doc_number] => 05818364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'High bit-rate huffman decoding' [patent_app_type] => 1 [patent_app_number] => 8/666964 [patent_app_country] => US [patent_app_date] => 1996-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3951 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818364.pdf [firstpage_image] =>[orig_patent_app_number] => 666964 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/666964
High bit-rate huffman decoding Jun 18, 1996 Issued
Array ( [id] => 3840346 [patent_doc_number] => 05815102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Delta sigma pwm dac to reduce switching' [patent_app_type] => 1 [patent_app_number] => 8/662873 [patent_app_country] => US [patent_app_date] => 1996-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 6151 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815102.pdf [firstpage_image] =>[orig_patent_app_number] => 662873 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/662873
Delta sigma pwm dac to reduce switching Jun 11, 1996 Issued
Array ( [id] => 3886588 [patent_doc_number] => 05748133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Analog to digital converter' [patent_app_type] => 1 [patent_app_number] => 8/662934 [patent_app_country] => US [patent_app_date] => 1996-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 47 [patent_no_of_words] => 11136 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748133.pdf [firstpage_image] =>[orig_patent_app_number] => 662934 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/662934
Analog to digital converter Jun 11, 1996 Issued
Array ( [id] => 3882736 [patent_doc_number] => 05764167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Compression and decompression of runs of ones and zeros in groups that progressively increase in size within each run' [patent_app_type] => 1 [patent_app_number] => 8/652068 [patent_app_country] => US [patent_app_date] => 1996-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3541 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764167.pdf [firstpage_image] =>[orig_patent_app_number] => 652068 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/652068
Compression and decompression of runs of ones and zeros in groups that progressively increase in size within each run May 22, 1996 Issued
08/651976 ANALOG-TO-DIGITAL CONVERTER WITH SIGMA-DELTA MODULATOR AND INTERNAL QUANTIZATION ERROR CORRECTION May 20, 1996 Abandoned
Array ( [id] => 3783868 [patent_doc_number] => 05757303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Multi-bit A/D converter having reduced circuitry' [patent_app_type] => 1 [patent_app_number] => 8/649063 [patent_app_country] => US [patent_app_date] => 1996-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2345 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757303.pdf [firstpage_image] =>[orig_patent_app_number] => 649063 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/649063
Multi-bit A/D converter having reduced circuitry May 15, 1996 Issued
Array ( [id] => 3882858 [patent_doc_number] => 05764174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Switch architecture for R/2R digital to analog converters' [patent_app_type] => 1 [patent_app_number] => 8/645675 [patent_app_country] => US [patent_app_date] => 1996-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6839 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764174.pdf [firstpage_image] =>[orig_patent_app_number] => 645675 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/645675
Switch architecture for R/2R digital to analog converters May 13, 1996 Issued
Array ( [id] => 3786217 [patent_doc_number] => 05818374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Switched current delta-sigma modulator' [patent_app_type] => 1 [patent_app_number] => 8/646970 [patent_app_country] => US [patent_app_date] => 1996-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2393 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818374.pdf [firstpage_image] =>[orig_patent_app_number] => 646970 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/646970
Switched current delta-sigma modulator May 7, 1996 Issued
Array ( [id] => 3767996 [patent_doc_number] => 05742244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Nonlinear run-length coding' [patent_app_type] => 1 [patent_app_number] => 8/636075 [patent_app_country] => US [patent_app_date] => 1996-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 4770 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742244.pdf [firstpage_image] =>[orig_patent_app_number] => 636075 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/636075
Nonlinear run-length coding Apr 21, 1996 Issued
Array ( [id] => 4165346 [patent_doc_number] => 06104325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'System and methods for compressing user settings based on default values' [patent_app_type] => 1 [patent_app_number] => 8/632829 [patent_app_country] => US [patent_app_date] => 1996-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 78 [patent_no_of_words] => 19606 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104325.pdf [firstpage_image] =>[orig_patent_app_number] => 632829 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/632829
System and methods for compressing user settings based on default values Apr 15, 1996 Issued
Array ( [id] => 3778972 [patent_doc_number] => 05774078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Single merging bit DC-suppressed run length limited coding' [patent_app_type] => 1 [patent_app_number] => 8/628167 [patent_app_country] => US [patent_app_date] => 1996-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8293 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774078.pdf [firstpage_image] =>[orig_patent_app_number] => 628167 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/628167
Single merging bit DC-suppressed run length limited coding Apr 4, 1996 Issued
Array ( [id] => 3883867 [patent_doc_number] => 05825316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Method for the self-calibration of an A/D or D/A converter in which the weighted references of the at least one main network are partially calibrated once per calibration cycle' [patent_app_type] => 1 [patent_app_number] => 8/627968 [patent_app_country] => US [patent_app_date] => 1996-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2993 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825316.pdf [firstpage_image] =>[orig_patent_app_number] => 627968 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/627968
Method for the self-calibration of an A/D or D/A converter in which the weighted references of the at least one main network are partially calibrated once per calibration cycle Apr 3, 1996 Issued
Array ( [id] => 3735637 [patent_doc_number] => 05703582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'DAC with feedback control for current source bias during non-display period' [patent_app_type] => 1 [patent_app_number] => 8/627663 [patent_app_country] => US [patent_app_date] => 1996-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5508 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703582.pdf [firstpage_image] =>[orig_patent_app_number] => 627663 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/627663
DAC with feedback control for current source bias during non-display period Mar 31, 1996 Issued
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