Search

Robert Skudy

Examiner (ID: 9509)

Most Active Art Unit
2102
Art Unit(s)
2101, 2102, 2105, 2899, 3201
Total Applications
1603
Issued Applications
1425
Pending Applications
7
Abandoned Applications
171

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17196085 [patent_doc_number] => 11164852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Method of forming package structure [patent_app_type] => utility [patent_app_number] => 16/272973 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 9140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16272973 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/272973
Method of forming package structure Feb 10, 2019 Issued
Array ( [id] => 16432994 [patent_doc_number] => 10833091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Ferroelectric memories [patent_app_type] => utility [patent_app_number] => 16/270706 [patent_app_country] => US [patent_app_date] => 2019-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4113 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16270706 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/270706
Ferroelectric memories Feb 7, 2019 Issued
Array ( [id] => 16241753 [patent_doc_number] => 20200258987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => TRANSISTOR WITH FIELD PLATE OVER TAPERED TRENCH ISOLATION [patent_app_type] => utility [patent_app_number] => 16/270729 [patent_app_country] => US [patent_app_date] => 2019-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16270729 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/270729
Transistor with field plate over tapered trench isolation Feb 7, 2019 Issued
Array ( [id] => 16280162 [patent_doc_number] => 10763203 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-01 [patent_title] => Conductive trace design for smart card [patent_app_type] => utility [patent_app_number] => 16/270607 [patent_app_country] => US [patent_app_date] => 2019-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3656 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16270607 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/270607
Conductive trace design for smart card Feb 7, 2019 Issued
Array ( [id] => 16432824 [patent_doc_number] => 10832920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Insulator semiconductor device-structure [patent_app_type] => utility [patent_app_number] => 16/269794 [patent_app_country] => US [patent_app_date] => 2019-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5246 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16269794 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/269794
Insulator semiconductor device-structure Feb 6, 2019 Issued
Array ( [id] => 14413983 [patent_doc_number] => 20190172835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/264558 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16264558 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/264558
Semiconductor device and manufacturing method thereof Jan 30, 2019 Issued
Array ( [id] => 15077671 [patent_doc_number] => 10468335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Bipolar transistor, semiconductor device, and bipolar transistor manufacturing method [patent_app_type] => utility [patent_app_number] => 16/263193 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6733 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16263193 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/263193
Bipolar transistor, semiconductor device, and bipolar transistor manufacturing method Jan 30, 2019 Issued
Array ( [id] => 15922527 [patent_doc_number] => 10658513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Formation of FinFET junction [patent_app_type] => utility [patent_app_number] => 16/261709 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4227 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16261709 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/261709
Formation of FinFET junction Jan 29, 2019 Issued
Array ( [id] => 16677433 [patent_doc_number] => 20210066199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => Electronic Device [patent_app_type] => utility [patent_app_number] => 16/961078 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16961078 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/961078
Electronic device Jan 29, 2019 Issued
Array ( [id] => 16180655 [patent_doc_number] => 20200227624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => MAGNETIC SHIELDING STRUCTURE FOR MRAM ARRAY [patent_app_type] => utility [patent_app_number] => 16/246925 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16246925 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/246925
Magnetic shielding structure for MRAM array Jan 13, 2019 Issued
Array ( [id] => 14588087 [patent_doc_number] => 20190221652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => SEMICONDUCTOR ELECTRONIC DEVICE WITH TRENCH GATE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/247358 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16247358 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/247358
SEMICONDUCTOR ELECTRONIC DEVICE WITH TRENCH GATE AND MANUFACTURING METHOD THEREOF Jan 13, 2019 Abandoned
Array ( [id] => 14631681 [patent_doc_number] => 20190229212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => LDMOS Transistor And Method For Manufacturing The Same [patent_app_type] => utility [patent_app_number] => 16/247007 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16247007 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/247007
LDMOS transistor and method for manufacturing the same Jan 13, 2019 Issued
Array ( [id] => 14631473 [patent_doc_number] => 20190229106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/247039 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16247039 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/247039
Semiconductor device Jan 13, 2019 Issued
Array ( [id] => 16638045 [patent_doc_number] => 10916560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Crenellated charge storage structures for 3D NAND [patent_app_type] => utility [patent_app_number] => 16/247079 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 8005 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16247079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/247079
Crenellated charge storage structures for 3D NAND Jan 13, 2019 Issued
Array ( [id] => 16653606 [patent_doc_number] => 10930799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Semiconductor die with buried capacitor, and method of manufacturing the semiconductor die [patent_app_type] => utility [patent_app_number] => 16/246945 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 6362 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16246945 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/246945
Semiconductor die with buried capacitor, and method of manufacturing the semiconductor die Jan 13, 2019 Issued
Array ( [id] => 17772661 [patent_doc_number] => 11404615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Light emitting device and method of manufacturing light emitting device [patent_app_type] => utility [patent_app_number] => 16/246679 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 9763 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16246679 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/246679
Light emitting device and method of manufacturing light emitting device Jan 13, 2019 Issued
Array ( [id] => 16187221 [patent_doc_number] => 10720563 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-21 [patent_title] => Quantum processor design to increase control footprint [patent_app_type] => utility [patent_app_number] => 16/247377 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16247377 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/247377
Quantum processor design to increase control footprint Jan 13, 2019 Issued
Array ( [id] => 16384794 [patent_doc_number] => 10809627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Mask, related display device, and related exposure method for manufacturing display device [patent_app_type] => utility [patent_app_number] => 16/245311 [patent_app_country] => US [patent_app_date] => 2019-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9799 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16245311 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/245311
Mask, related display device, and related exposure method for manufacturing display device Jan 10, 2019 Issued
Array ( [id] => 14317665 [patent_doc_number] => 20190148536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION METAL OXIDE SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD FOR THE SAME [patent_app_type] => utility [patent_app_number] => 16/245681 [patent_app_country] => US [patent_app_date] => 2019-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16245681 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/245681
Semiconductor device having super junction metal oxide semiconductor structure and fabrication method for the same Jan 10, 2019 Issued
Array ( [id] => 14317665 [patent_doc_number] => 20190148536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION METAL OXIDE SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD FOR THE SAME [patent_app_type] => utility [patent_app_number] => 16/245681 [patent_app_country] => US [patent_app_date] => 2019-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16245681 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/245681
Semiconductor device having super junction metal oxide semiconductor structure and fabrication method for the same Jan 10, 2019 Issued
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