Search

Robert Song

Examiner (ID: 15638)

Most Active Art Unit
3102
Art Unit(s)
2203, 3102, 3106
Total Applications
1719
Issued Applications
1671
Pending Applications
1
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1453698 [patent_doc_number] => 06461985 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers' [patent_app_type] => B1 [patent_app_number] => 09/393542 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3449 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/461/06461985.pdf [firstpage_image] =>[orig_patent_app_number] => 09393542 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/393542
Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers Sep 9, 1999 Issued
Array ( [id] => 7063542 [patent_doc_number] => 20010042919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => new [patent_app_number] => 09/387477 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3656 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20010042919.pdf [firstpage_image] =>[orig_patent_app_number] => 09387477 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387477
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Aug 31, 1999 Abandoned
Array ( [id] => 694785 [patent_doc_number] => 07071060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-04 [patent_title] => 'EEPROM with split gate source side infection with sidewall spacers' [patent_app_type] => utility [patent_app_number] => 09/386170 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 39 [patent_no_of_words] => 14265 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/071/07071060.pdf [firstpage_image] =>[orig_patent_app_number] => 09386170 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/386170
EEPROM with split gate source side infection with sidewall spacers Aug 30, 1999 Issued
Array ( [id] => 1110986 [patent_doc_number] => 06806166 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Substrate removal as a function of emitted photons at the back side of a semiconductor chip' [patent_app_type] => B1 [patent_app_number] => 09/379047 [patent_app_country] => US [patent_app_date] => 1999-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2757 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806166.pdf [firstpage_image] =>[orig_patent_app_number] => 09379047 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/379047
Substrate removal as a function of emitted photons at the back side of a semiconductor chip Aug 22, 1999 Issued
Array ( [id] => 1376735 [patent_doc_number] => 06559076 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method of removing free halogen from a halogenated polymer insulating layer of a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/377070 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3436 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559076.pdf [firstpage_image] =>[orig_patent_app_number] => 09377070 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377070
Method of removing free halogen from a halogenated polymer insulating layer of a semiconductor device Aug 18, 1999 Issued
Array ( [id] => 1550450 [patent_doc_number] => 06399481 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method for forming resist pattern' [patent_app_type] => B1 [patent_app_number] => 09/368587 [patent_app_country] => US [patent_app_date] => 1999-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4634 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399481.pdf [firstpage_image] =>[orig_patent_app_number] => 09368587 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368587
Method for forming resist pattern Aug 4, 1999 Issued
Array ( [id] => 1385797 [patent_doc_number] => 06548359 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Asymmetrical devices for short gate length performance with disposable sidewall' [patent_app_type] => B1 [patent_app_number] => 09/368387 [patent_app_country] => US [patent_app_date] => 1999-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 17 [patent_no_of_words] => 2703 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548359.pdf [firstpage_image] =>[orig_patent_app_number] => 09368387 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368387
Asymmetrical devices for short gate length performance with disposable sidewall Aug 3, 1999 Issued
Array ( [id] => 1542816 [patent_doc_number] => 06372662 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method of oxidizing a silicon surface' [patent_app_type] => B1 [patent_app_number] => 09/356637 [patent_app_country] => US [patent_app_date] => 1999-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2478 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372662.pdf [firstpage_image] =>[orig_patent_app_number] => 09356637 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/356637
Method of oxidizing a silicon surface Jul 18, 1999 Issued
Array ( [id] => 7636665 [patent_doc_number] => 06379990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method of fabricating a micromechanical semiconductor configuration' [patent_app_type] => B1 [patent_app_number] => 09/348160 [patent_app_country] => US [patent_app_date] => 1999-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2148 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/379/06379990.pdf [firstpage_image] =>[orig_patent_app_number] => 09348160 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/348160
Method of fabricating a micromechanical semiconductor configuration Jul 5, 1999 Issued
Array ( [id] => 1382252 [patent_doc_number] => 06551913 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Method for fabricating a gate electrode of a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/343480 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1493 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/551/06551913.pdf [firstpage_image] =>[orig_patent_app_number] => 09343480 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343480
Method for fabricating a gate electrode of a semiconductor device Jun 29, 1999 Issued
Array ( [id] => 7093124 [patent_doc_number] => 20010034090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'METHODS FOR FORMING A GATE DIELECTRIC FILM OF A SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/345297 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1838 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034090.pdf [firstpage_image] =>[orig_patent_app_number] => 09345297 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345297
METHODS FOR FORMING A GATE DIELECTRIC FILM OF A SEMICONDUCTOR DEVICE Jun 29, 1999 Abandoned
Array ( [id] => 4293330 [patent_doc_number] => 06197621 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Custom laser conductor linkage for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/336270 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4258 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197621.pdf [firstpage_image] =>[orig_patent_app_number] => 336270 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/336270
Custom laser conductor linkage for integrated circuits Jun 17, 1999 Issued
Array ( [id] => 4327189 [patent_doc_number] => 06319808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Ohmic contact to semiconductor devices and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/325240 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2865 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319808.pdf [firstpage_image] =>[orig_patent_app_number] => 325240 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/325240
Ohmic contact to semiconductor devices and method of manufacturing the same Jun 2, 1999 Issued
Array ( [id] => 1542680 [patent_doc_number] => 06372613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method of manufacturing a gate electrode with low resistance metal layer remote from a semiconductor' [patent_app_type] => B2 [patent_app_number] => 09/304520 [patent_app_country] => US [patent_app_date] => 1999-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 4688 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372613.pdf [firstpage_image] =>[orig_patent_app_number] => 09304520 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304520
Method of manufacturing a gate electrode with low resistance metal layer remote from a semiconductor May 3, 1999 Issued
Array ( [id] => 4310407 [patent_doc_number] => 06316328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Fabrication method for semiconductor device utilizing parallel alignment slits' [patent_app_type] => 1 [patent_app_number] => 9/265467 [patent_app_country] => US [patent_app_date] => 1999-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 7537 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316328.pdf [firstpage_image] =>[orig_patent_app_number] => 265467 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/265467
Fabrication method for semiconductor device utilizing parallel alignment slits Mar 9, 1999 Issued
Array ( [id] => 4357564 [patent_doc_number] => 06174807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Method of controlling gate dopant penetration and diffusion in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/260947 [patent_app_country] => US [patent_app_date] => 1999-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2375 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174807.pdf [firstpage_image] =>[orig_patent_app_number] => 260947 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/260947
Method of controlling gate dopant penetration and diffusion in a semiconductor device Mar 1, 1999 Issued
Array ( [id] => 4238434 [patent_doc_number] => 06080653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component' [patent_app_type] => 1 [patent_app_number] => 9/257880 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1749 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080653.pdf [firstpage_image] =>[orig_patent_app_number] => 257880 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/257880
Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component Feb 24, 1999 Issued
Array ( [id] => 4381785 [patent_doc_number] => 06261947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Formation of electrical contacts to conductive elements in the fabrication of semiconductor integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/252697 [patent_app_country] => US [patent_app_date] => 1999-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 4252 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261947.pdf [firstpage_image] =>[orig_patent_app_number] => 252697 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252697
Formation of electrical contacts to conductive elements in the fabrication of semiconductor integrated circuits Feb 17, 1999 Issued
Array ( [id] => 1381626 [patent_doc_number] => 06551876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-22 [patent_title] => 'Processing methods of forming an electrically conductive plug to a node location' [patent_app_type] => B2 [patent_app_number] => 09/251219 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 2637 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/551/06551876.pdf [firstpage_image] =>[orig_patent_app_number] => 09251219 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251219
Processing methods of forming an electrically conductive plug to a node location Feb 15, 1999 Issued
Array ( [id] => 1478128 [patent_doc_number] => 06451674 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method for introducing impurity into a semiconductor substrate without negative charge buildup phenomenon' [patent_app_type] => B1 [patent_app_number] => 09/243797 [patent_app_country] => US [patent_app_date] => 1999-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6044 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451674.pdf [firstpage_image] =>[orig_patent_app_number] => 09243797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/243797
Method for introducing impurity into a semiconductor substrate without negative charge buildup phenomenon Feb 2, 1999 Issued
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