
Robert Song
Examiner (ID: 15638)
| Most Active Art Unit | 3102 |
| Art Unit(s) | 2203, 3102, 3106 |
| Total Applications | 1719 |
| Issued Applications | 1671 |
| Pending Applications | 1 |
| Abandoned Applications | 47 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1453698
[patent_doc_number] => 06461985
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-08
[patent_title] => 'Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers'
[patent_app_type] => B1
[patent_app_number] => 09/393542
[patent_app_country] => US
[patent_app_date] => 1999-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3449
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[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/461/06461985.pdf
[firstpage_image] =>[orig_patent_app_number] => 09393542
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/393542 | Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers | Sep 9, 1999 | Issued |
Array
(
[id] => 7063542
[patent_doc_number] => 20010042919
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-22
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => new
[patent_app_number] => 09/387477
[patent_app_country] => US
[patent_app_date] => 1999-09-01
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0042/20010042919.pdf
[firstpage_image] =>[orig_patent_app_number] => 09387477
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/387477 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Aug 31, 1999 | Abandoned |
Array
(
[id] => 694785
[patent_doc_number] => 07071060
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-07-04
[patent_title] => 'EEPROM with split gate source side infection with sidewall spacers'
[patent_app_type] => utility
[patent_app_number] => 09/386170
[patent_app_country] => US
[patent_app_date] => 1999-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
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[pdf_file] => patents/07/071/07071060.pdf
[firstpage_image] =>[orig_patent_app_number] => 09386170
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/386170 | EEPROM with split gate source side infection with sidewall spacers | Aug 30, 1999 | Issued |
Array
(
[id] => 1110986
[patent_doc_number] => 06806166
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-10-19
[patent_title] => 'Substrate removal as a function of emitted photons at the back side of a semiconductor chip'
[patent_app_type] => B1
[patent_app_number] => 09/379047
[patent_app_country] => US
[patent_app_date] => 1999-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2757
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[pdf_file] => patents/06/806/06806166.pdf
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Array
(
[id] => 1376735
[patent_doc_number] => 06559076
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-06
[patent_title] => 'Method of removing free halogen from a halogenated polymer insulating layer of a semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/377070
[patent_app_country] => US
[patent_app_date] => 1999-08-19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/377070 | Method of removing free halogen from a halogenated polymer insulating layer of a semiconductor device | Aug 18, 1999 | Issued |
Array
(
[id] => 1550450
[patent_doc_number] => 06399481
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[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'Method for forming resist pattern'
[patent_app_type] => B1
[patent_app_number] => 09/368587
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Array
(
[id] => 1385797
[patent_doc_number] => 06548359
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[patent_issue_date] => 2003-04-15
[patent_title] => 'Asymmetrical devices for short gate length performance with disposable sidewall'
[patent_app_type] => B1
[patent_app_number] => 09/368387
[patent_app_country] => US
[patent_app_date] => 1999-08-04
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[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/548/06548359.pdf
[firstpage_image] =>[orig_patent_app_number] => 09368387
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/368387 | Asymmetrical devices for short gate length performance with disposable sidewall | Aug 3, 1999 | Issued |
Array
(
[id] => 1542816
[patent_doc_number] => 06372662
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-16
[patent_title] => 'Method of oxidizing a silicon surface'
[patent_app_type] => B1
[patent_app_number] => 09/356637
[patent_app_country] => US
[patent_app_date] => 1999-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2478
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[pdf_file] => patents/06/372/06372662.pdf
[firstpage_image] =>[orig_patent_app_number] => 09356637
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/356637 | Method of oxidizing a silicon surface | Jul 18, 1999 | Issued |
Array
(
[id] => 7636665
[patent_doc_number] => 06379990
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-30
[patent_title] => 'Method of fabricating a micromechanical semiconductor configuration'
[patent_app_type] => B1
[patent_app_number] => 09/348160
[patent_app_country] => US
[patent_app_date] => 1999-07-06
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[pdf_file] => patents/06/379/06379990.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/348160 | Method of fabricating a micromechanical semiconductor configuration | Jul 5, 1999 | Issued |
Array
(
[id] => 1382252
[patent_doc_number] => 06551913
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[patent_kind] => B1
[patent_issue_date] => 2003-04-22
[patent_title] => 'Method for fabricating a gate electrode of a semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/343480
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Array
(
[id] => 7093124
[patent_doc_number] => 20010034090
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[patent_issue_date] => 2001-10-25
[patent_title] => 'METHODS FOR FORMING A GATE DIELECTRIC FILM OF A SEMICONDUCTOR DEVICE'
[patent_app_type] => new
[patent_app_number] => 09/345297
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Array
(
[id] => 4293330
[patent_doc_number] => 06197621
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[patent_kind] => NA
[patent_issue_date] => 2001-03-06
[patent_title] => 'Custom laser conductor linkage for integrated circuits'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/336270 | Custom laser conductor linkage for integrated circuits | Jun 17, 1999 | Issued |
Array
(
[id] => 4327189
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Array
(
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[patent_title] => 'Method of manufacturing a gate electrode with low resistance metal layer remote from a semiconductor'
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Array
(
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Array
(
[id] => 4357564
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/260947 | Method of controlling gate dopant penetration and diffusion in a semiconductor device | Mar 1, 1999 | Issued |
Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/243797 | Method for introducing impurity into a semiconductor substrate without negative charge buildup phenomenon | Feb 2, 1999 | Issued |