Robert Stockton Jones Jr.

Array ( [id] => 3645996 [patent_doc_number] => 05610955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Circuit for generating a spread spectrum clock' [patent_app_type] => 1 [patent_app_number] => 8/563327 [patent_app_country] => US [patent_app_date] => 1995-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1878 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/610/05610955.pdf [firstpage_image] =>[orig_patent_app_number] => 563327 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3528109 [patent_doc_number] => 05577074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Combined clock recovery/frequency stabilization loop' [patent_app_type] => 1 [patent_app_number] => 8/546028 [patent_app_country] => US [patent_app_date] => 1995-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3888 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/577/05577074.pdf [firstpage_image] =>[orig_patent_app_number] => 546028 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3700207 [patent_doc_number] => 05604774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Fully secondary DPLL and destuffing circuit employing same' [patent_app_type] => 1 [patent_app_number] => 8/527353 [patent_app_country] => US [patent_app_date] => 1995-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2480 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604774.pdf [firstpage_image] =>[orig_patent_app_number] => 527353 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3675152 [patent_doc_number] => 05598446 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Clock extraction of a clock signal using rising and falling edges of a received transmission signal' [patent_app_type] => 1 [patent_app_number] => 8/525999 [patent_app_country] => US [patent_app_date] => 1995-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3853 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598446.pdf [firstpage_image] =>[orig_patent_app_number] => 525999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3599260 [patent_doc_number] => 05550879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Motor current signal processor including phase locked and delta modulated loops' [patent_app_type] => 1 [patent_app_number] => 8/521501 [patent_app_country] => US [patent_app_date] => 1995-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1954 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/550/05550879.pdf [firstpage_image] =>[orig_patent_app_number] => 521501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3599274 [patent_doc_number] => 05550880 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Motor current signal processor using analog substraction of an estimated largest sine wave component' [patent_app_type] => 1 [patent_app_number] => 8/521503 [patent_app_country] => US [patent_app_date] => 1995-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1326 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/550/05550880.pdf [firstpage_image] =>[orig_patent_app_number] => 521503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3583930 [patent_doc_number] => 05539786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Digital circuit for generating a clock signal' [patent_app_type] => 1 [patent_app_number] => 8/521385 [patent_app_country] => US [patent_app_date] => 1995-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1829 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539786.pdf [firstpage_image] =>[orig_patent_app_number] => 521385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3528180 [patent_doc_number] => 05577079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Phase comparing circuit and PLL circuit' [patent_app_type] => 1 [patent_app_number] => 8/504470 [patent_app_country] => US [patent_app_date] => 1995-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 17258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/577/05577079.pdf [firstpage_image] =>[orig_patent_app_number] => 504470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3601347 [patent_doc_number] => 05586143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Apparatus and method for processing data signals in a digital receiver' [patent_app_type] => 1 [patent_app_number] => 8/499978 [patent_app_country] => US [patent_app_date] => 1995-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2370 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586143.pdf [firstpage_image] =>[orig_patent_app_number] => 499978 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3636477 [patent_doc_number] => 05608765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-04 [patent_title] => 'Radio frame synchronization system' [patent_app_type] => 1 [patent_app_number] => 8/500359 [patent_app_country] => US [patent_app_date] => 1995-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1766 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/608/05608765.pdf [firstpage_image] =>[orig_patent_app_number] => 500359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3503812 [patent_doc_number] => 05537449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Clock synchronizing circuitry having a fast tuning circuit' [patent_app_type] => 1 [patent_app_number] => 8/495973 [patent_app_country] => US [patent_app_date] => 1995-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3243 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537449.pdf [firstpage_image] =>[orig_patent_app_number] => 495973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3619076 [patent_doc_number] => 05590154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Equalizer circuit and a method for equalizing a continuous signal' [patent_app_type] => 1 [patent_app_number] => 8/494424 [patent_app_country] => US [patent_app_date] => 1995-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4754 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590154.pdf [firstpage_image] =>[orig_patent_app_number] => 494424 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3564201 [patent_doc_number] => 05574757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Phase-locked loop circuit having a timing holdover function' [patent_app_type] => 1 [patent_app_number] => 8/494564 [patent_app_country] => US [patent_app_date] => 1995-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4418 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574757.pdf [firstpage_image] =>[orig_patent_app_number] => 494564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3537714 [patent_doc_number] => 05528635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-18 [patent_title] => 'Synchronization detecting circuit' [patent_app_type] => 1 [patent_app_number] => 8/492760 [patent_app_country] => US [patent_app_date] => 1995-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2504 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/528/05528635.pdf [firstpage_image] =>[orig_patent_app_number] => 492760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3558615 [patent_doc_number] => 05555546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Apparatus for decoding a DPCM encoded signal' [patent_app_type] => 1 [patent_app_number] => 8/488997 [patent_app_country] => US [patent_app_date] => 1995-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3369 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 472 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/555/05555546.pdf [firstpage_image] =>[orig_patent_app_number] => 488997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3597816 [patent_doc_number] => 05553103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Circuit including a subtractor, an adder, and first and second clocked registers connected in series' [patent_app_type] => 1 [patent_app_number] => 8/484764 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 7459 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/553/05553103.pdf [firstpage_image] =>[orig_patent_app_number] => 484764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3645897 [patent_doc_number] => 05610948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Digital demodulation apparatus' [patent_app_type] => 1 [patent_app_number] => 8/447889 [patent_app_country] => US [patent_app_date] => 1995-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 8425 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/610/05610948.pdf [firstpage_image] =>[orig_patent_app_number] => 447889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3634727 [patent_doc_number] => 05602884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Digital phase locked loop' [patent_app_type] => 1 [patent_app_number] => 8/440939 [patent_app_country] => US [patent_app_date] => 1995-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 6379 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602884.pdf [firstpage_image] =>[orig_patent_app_number] => 440939 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3675039 [patent_doc_number] => 05598438 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Cordless telecommunication apparatus' [patent_app_type] => 1 [patent_app_number] => 8/428142 [patent_app_country] => US [patent_app_date] => 1995-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4615 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598438.pdf [firstpage_image] =>[orig_patent_app_number] => 428142 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3559403 [patent_doc_number] => 05546433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Digital phase lock loop having frequency offset cancellation circuitry' [patent_app_type] => 1 [patent_app_number] => 8/408027 [patent_app_country] => US [patent_app_date] => 1995-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2226 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546433.pdf [firstpage_image] =>[orig_patent_app_number] => 408027 [rel_patent_id] =>[rel_patent_doc_number] =>)