Search

Robert T. Huber

Examiner (ID: 18933)

Most Active Art Unit
2892
Art Unit(s)
2892
Total Applications
651
Issued Applications
367
Pending Applications
0
Abandoned Applications
285

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9515344 [patent_doc_number] => 20140151836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'OPTICAL SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/173590 [patent_app_country] => US [patent_app_date] => 2014-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5488 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14173590 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/173590
OPTICAL SEMICONDUCTOR APPARATUS Feb 4, 2014 Abandoned
Array ( [id] => 9556651 [patent_doc_number] => 20140174363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'FILM FORMING APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/170694 [patent_app_country] => US [patent_app_date] => 2014-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9595 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14170694 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/170694
FILM FORMING APPARATUS Feb 2, 2014 Abandoned
Array ( [id] => 10329132 [patent_doc_number] => 20150214136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING LEADFRAME WITH PRESSURE-ABSORBING PAD STRAPS' [patent_app_type] => utility [patent_app_number] => 14/168720 [patent_app_country] => US [patent_app_date] => 2014-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2895 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14168720 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/168720
SEMICONDUCTOR DEVICE HAVING LEADFRAME WITH PRESSURE-ABSORBING PAD STRAPS Jan 29, 2014 Abandoned
Array ( [id] => 10331062 [patent_doc_number] => 20150216066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE HAVING IMPROVED COPLANARITY' [patent_app_type] => utility [patent_app_number] => 14/166682 [patent_app_country] => US [patent_app_date] => 2014-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166682 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/166682
INTEGRATED CIRCUIT PACKAGE HAVING IMPROVED COPLANARITY Jan 27, 2014 Abandoned
Array ( [id] => 10329411 [patent_doc_number] => 20150214416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'METHOD OF PACKAGE FOR SENSOR CHIP' [patent_app_type] => utility [patent_app_number] => 14/166668 [patent_app_country] => US [patent_app_date] => 2014-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2024 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166668 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/166668
METHOD OF PACKAGE FOR SENSOR CHIP Jan 27, 2014 Abandoned
Array ( [id] => 9488333 [patent_doc_number] => 20140138739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'INTEGRATED POWER DEVICE ON A SEMICONDUCTOR SUBSTRATE HAVING AN IMPROVED TRENCH GATE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/166075 [patent_app_country] => US [patent_app_date] => 2014-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8290 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166075 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/166075
Integrated power device on a semiconductor substrate having an improved trench gate structure Jan 27, 2014 Issued
Array ( [id] => 10329240 [patent_doc_number] => 20150214244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'STRUCTURE AND PROCESS TO DECOUPLE DEEP TRENCH CAPACITORS AND WELL ISOLATION' [patent_app_type] => utility [patent_app_number] => 14/166155 [patent_app_country] => US [patent_app_date] => 2014-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4180 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166155 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/166155
STRUCTURE AND PROCESS TO DECOUPLE DEEP TRENCH CAPACITORS AND WELL ISOLATION Jan 27, 2014 Abandoned
Array ( [id] => 11770378 [patent_doc_number] => 09379075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-28 [patent_title] => 'Semiconductor device with bump stop structure' [patent_app_type] => utility [patent_app_number] => 14/166531 [patent_app_country] => US [patent_app_date] => 2014-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14166531 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/166531
Semiconductor device with bump stop structure Jan 27, 2014 Issued
Array ( [id] => 10329200 [patent_doc_number] => 20150214204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'Electronic Device and Method for Fabricating an Electronic Device' [patent_app_type] => utility [patent_app_number] => 14/165769 [patent_app_country] => US [patent_app_date] => 2014-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4924 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14165769 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/165769
Electronic Device and Method for Fabricating an Electronic Device Jan 27, 2014 Abandoned
Array ( [id] => 9488302 [patent_doc_number] => 20140138709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'SILICON CARBIDE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/163209 [patent_app_country] => US [patent_app_date] => 2014-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5000 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14163209 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/163209
SILICON CARBIDE SUBSTRATE Jan 23, 2014 Abandoned
Array ( [id] => 9883171 [patent_doc_number] => 08969938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Method and structure for forming on-chip high quality capacitors with ETSOI transistors' [patent_app_type] => utility [patent_app_number] => 14/154202 [patent_app_country] => US [patent_app_date] => 2014-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3871 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14154202 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/154202
Method and structure for forming on-chip high quality capacitors with ETSOI transistors Jan 13, 2014 Issued
Array ( [id] => 9460526 [patent_doc_number] => 20140124952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'ARRAY AND MOAT ISOLATION STRUCTURES AND METHOD OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 14/149280 [patent_app_country] => US [patent_app_date] => 2014-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4903 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14149280 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/149280
Array and moat isolation structures and method of manufacture Jan 6, 2014 Issued
Array ( [id] => 10303044 [patent_doc_number] => 20150188044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'Embedded Resistors for Resistive Random Access Memory Cells' [patent_app_type] => utility [patent_app_number] => 14/140668 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8050 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14140668 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/140668
Embedded Resistors for Resistive Random Access Memory Cells Dec 25, 2013 Abandoned
Array ( [id] => 10302577 [patent_doc_number] => 20150187577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'METHOD AND STRUCTURE FOR MULTIGATE FINFET DEVICE EPI-EXTENSION JUNCTION CONTROL BY HYDROGEN TREATMENT' [patent_app_type] => utility [patent_app_number] => 14/141051 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141051 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/141051
Method and structure for multigate FinFET device epi-extension junction control by hydrogen treatment Dec 25, 2013 Issued
Array ( [id] => 10303043 [patent_doc_number] => 20150188043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'Embedded Resistors for Resistive Random Access Memory Cells' [patent_app_type] => utility [patent_app_number] => 14/140660 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9119 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14140660 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/140660
Embedded resistors for resistive random access memory cells Dec 25, 2013 Issued
Array ( [id] => 10302900 [patent_doc_number] => 20150187900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'COMPOSITE MATERIALS FOR USE IN SEMICONDUCTOR COMPONENTS' [patent_app_type] => utility [patent_app_number] => 14/140629 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14140629 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/140629
COMPOSITE MATERIALS FOR USE IN SEMICONDUCTOR COMPONENTS Dec 25, 2013 Abandoned
Array ( [id] => 10303045 [patent_doc_number] => 20150188045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'Stacked Bi-layer as the low power switchable RRAM' [patent_app_type] => utility [patent_app_number] => 14/140683 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8859 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14140683 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/140683
Stacked bi-layer as the low power switchable RRAM Dec 25, 2013 Issued
Array ( [id] => 12574041 [patent_doc_number] => 10020275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Semiconductive packaging device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 14/140853 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 6437 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14140853 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/140853
Semiconductive packaging device and manufacturing method thereof Dec 25, 2013 Issued
Array ( [id] => 13667153 [patent_doc_number] => 10163754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Lid design for heat dissipation enhancement of die package [patent_app_type] => utility [patent_app_number] => 14/140692 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 35 [patent_no_of_words] => 5071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14140692 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/140692
Lid design for heat dissipation enhancement of die package Dec 25, 2013 Issued
Array ( [id] => 10302594 [patent_doc_number] => 20150187594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'Composite Structure for Gate Level Inter-Layer Dielectric' [patent_app_type] => utility [patent_app_number] => 14/141028 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141028 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/141028
Composite structure for gate level inter-layer dielectric Dec 25, 2013 Issued
Menu