Search

Robert T. Huber

Examiner (ID: 18933)

Most Active Art Unit
2892
Art Unit(s)
2892
Total Applications
651
Issued Applications
367
Pending Applications
0
Abandoned Applications
285

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12229834 [patent_doc_number] => 09917083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Semiconductor device with an upper surface of a substrate at different levels and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/858142 [patent_app_country] => US [patent_app_date] => 2013-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 6834 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 467 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13858142 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/858142
Semiconductor device with an upper surface of a substrate at different levels and method of manufacturing the same Apr 7, 2013 Issued
Array ( [id] => 9327759 [patent_doc_number] => 20140054541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'METHOD OF MANUFACTURING QUANTUM DOT DEVICE, QUANTUM DOT DEVICE MANUFACTURED BY USING THE METHOD, AND METHOD OF MEASURING ELECTRON MOBILITY OF QUANTUM DOT DEVICE' [patent_app_type] => utility [patent_app_number] => 13/858136 [patent_app_country] => US [patent_app_date] => 2013-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4860 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13858136 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/858136
METHOD OF MANUFACTURING QUANTUM DOT DEVICE, QUANTUM DOT DEVICE MANUFACTURED BY USING THE METHOD, AND METHOD OF MEASURING ELECTRON MOBILITY OF QUANTUM DOT DEVICE Apr 7, 2013 Abandoned
Array ( [id] => 9188885 [patent_doc_number] => 20130328200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'DIRECT BONDED COPPER SUBSTRATE AND POWER SEMICONDUCTOR MODULE' [patent_app_type] => utility [patent_app_number] => 13/858290 [patent_app_country] => US [patent_app_date] => 2013-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1956 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13858290 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/858290
DIRECT BONDED COPPER SUBSTRATE AND POWER SEMICONDUCTOR MODULE Apr 7, 2013 Abandoned
Array ( [id] => 11360335 [patent_doc_number] => 09536993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Thin film transistor and method for manufacturing thin film transistor' [patent_app_type] => utility [patent_app_number] => 14/386811 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 40 [patent_no_of_words] => 18370 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14386811 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/386811
Thin film transistor and method for manufacturing thin film transistor Mar 17, 2013 Issued
Array ( [id] => 10888612 [patent_doc_number] => 08912607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Replacement metal gate structures providing independent control on work function and gate leakage current' [patent_app_type] => utility [patent_app_number] => 13/789018 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12826 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13789018 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/789018
Replacement metal gate structures providing independent control on work function and gate leakage current Mar 6, 2013 Issued
Array ( [id] => 9038353 [patent_doc_number] => 20130240991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 13/784709 [patent_app_country] => US [patent_app_date] => 2013-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11770 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13784709 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/784709
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME Mar 3, 2013 Abandoned
Array ( [id] => 9662875 [patent_doc_number] => 08809860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'III-V compound semiconductor material passivation with crystalline interlayer' [patent_app_type] => utility [patent_app_number] => 13/775968 [patent_app_country] => US [patent_app_date] => 2013-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4729 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13775968 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/775968
III-V compound semiconductor material passivation with crystalline interlayer Feb 24, 2013 Issued
Array ( [id] => 10080037 [patent_doc_number] => 09117893 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-08-25 [patent_title] => 'Tunneling transistor suitable for low voltage operation' [patent_app_type] => utility [patent_app_number] => 13/759478 [patent_app_country] => US [patent_app_date] => 2013-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 38 [patent_no_of_words] => 12913 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13759478 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/759478
Tunneling transistor suitable for low voltage operation Feb 4, 2013 Issued
Array ( [id] => 9183815 [patent_doc_number] => 08623747 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-07 [patent_title] => 'Silicon, aluminum oxide, aluminum nitride template for optoelectronic and power devices' [patent_app_type] => utility [patent_app_number] => 13/717182 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1564 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13717182 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/717182
Silicon, aluminum oxide, aluminum nitride template for optoelectronic and power devices Dec 16, 2012 Issued
Array ( [id] => 8826016 [patent_doc_number] => 20130127061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/716479 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6703 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13716479 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/716479
Integrated circuit having staggered bond pads and I/O cells Dec 16, 2012 Issued
Array ( [id] => 10016120 [patent_doc_number] => 09059141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Buried gate transistor' [patent_app_type] => utility [patent_app_number] => 13/665448 [patent_app_country] => US [patent_app_date] => 2012-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 5394 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13665448 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/665448
Buried gate transistor Oct 30, 2012 Issued
Array ( [id] => 10864525 [patent_doc_number] => 08890231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-18 [patent_title] => 'Nonvolatile semiconductor memory device with a narrowing charge storage layer' [patent_app_type] => utility [patent_app_number] => 13/603710 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 51 [patent_no_of_words] => 14093 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 367 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13603710 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/603710
Nonvolatile semiconductor memory device with a narrowing charge storage layer Sep 4, 2012 Issued
Array ( [id] => 9530589 [patent_doc_number] => 08754465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-17 [patent_title] => 'Semiconductor device with fixed charge layers' [patent_app_type] => utility [patent_app_number] => 13/603704 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 4170 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13603704 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/603704
Semiconductor device with fixed charge layers Sep 4, 2012 Issued
Array ( [id] => 8506583 [patent_doc_number] => 20120305991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'DEVICE HAVING SERIES-CONNECTED HIGH ELECTRON MOBILITY TRANSISTORS AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/584897 [patent_app_country] => US [patent_app_date] => 2012-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2982 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13584897 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/584897
DEVICE HAVING SERIES-CONNECTED HIGH ELECTRON MOBILITY TRANSISTORS AND MANUFACTURING METHOD THEREOF Aug 13, 2012 Abandoned
Array ( [id] => 8509777 [patent_doc_number] => 20120309186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/568465 [patent_app_country] => US [patent_app_date] => 2012-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2415 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13568465 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/568465
CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME Aug 6, 2012 Abandoned
Array ( [id] => 9889391 [patent_doc_number] => 08975650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Semiconductor light emitting device including a vertically arranged light transmitting layer and light emitting structure' [patent_app_type] => utility [patent_app_number] => 13/563328 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4951 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 543 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13563328 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/563328
Semiconductor light emitting device including a vertically arranged light transmitting layer and light emitting structure Jul 30, 2012 Issued
Array ( [id] => 8634708 [patent_doc_number] => 20130026511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'TRANSFER-BONDING METHOD FOR THE LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE ARRAY' [patent_app_type] => utility [patent_app_number] => 13/557231 [patent_app_country] => US [patent_app_date] => 2012-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6156 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13557231 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/557231
TRANSFER-BONDING METHOD FOR THE LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE ARRAY Jul 24, 2012 Abandoned
Array ( [id] => 10099887 [patent_doc_number] => 09136206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Copper contact plugs with barrier layers' [patent_app_type] => utility [patent_app_number] => 13/557592 [patent_app_country] => US [patent_app_date] => 2012-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 3727 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13557592 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/557592
Copper contact plugs with barrier layers Jul 24, 2012 Issued
Array ( [id] => 8634813 [patent_doc_number] => 20130026616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'POWER DEVICE PACKAGE MODULE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/557834 [patent_app_country] => US [patent_app_date] => 2012-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6365 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13557834 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/557834
POWER DEVICE PACKAGE MODULE AND MANUFACTURING METHOD THEREOF Jul 24, 2012 Abandoned
Array ( [id] => 11391803 [patent_doc_number] => 09553053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-24 [patent_title] => 'Bump structure for yield improvement' [patent_app_type] => utility [patent_app_number] => 13/558082 [patent_app_country] => US [patent_app_date] => 2012-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 52 [patent_no_of_words] => 4417 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13558082 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/558082
Bump structure for yield improvement Jul 24, 2012 Issued
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