Search

Robert T. Huber

Examiner (ID: 18933)

Most Active Art Unit
2892
Art Unit(s)
2892
Total Applications
651
Issued Applications
367
Pending Applications
0
Abandoned Applications
285

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9345563 [patent_doc_number] => 08664713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Integrated power device on a semiconductor substrate having an improved trench gate structure' [patent_app_type] => utility [patent_app_number] => 12/645255 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 8221 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12645255 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/645255
Integrated power device on a semiconductor substrate having an improved trench gate structure Dec 21, 2009 Issued
Array ( [id] => 6279892 [patent_doc_number] => 20100155721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/645433 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5002 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20100155721.pdf [firstpage_image] =>[orig_patent_app_number] => 12645433 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/645433
THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME Dec 21, 2009 Abandoned
Array ( [id] => 6304922 [patent_doc_number] => 20100068864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'APPARATUS AND METHOD FOR WAFER LEVEL FABRICATION OF HIGH VALUE INDUCTORS ON SEMICONDUCTOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/624259 [patent_app_country] => US [patent_app_date] => 2009-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2207 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20100068864.pdf [firstpage_image] =>[orig_patent_app_number] => 12624259 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/624259
Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits Nov 22, 2009 Issued
Array ( [id] => 4460340 [patent_doc_number] => 07879692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Programmable resistive memory cell with self-forming gap' [patent_app_type] => utility [patent_app_number] => 12/576099 [patent_app_country] => US [patent_app_date] => 2009-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6795 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/879/07879692.pdf [firstpage_image] =>[orig_patent_app_number] => 12576099 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/576099
Programmable resistive memory cell with self-forming gap Oct 7, 2009 Issued
Array ( [id] => 6027147 [patent_doc_number] => 20110079917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-07 [patent_title] => 'Interposer structure with passive component and method for fabricating same' [patent_app_type] => utility [patent_app_number] => 12/587482 [patent_app_country] => US [patent_app_date] => 2009-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3836 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20110079917.pdf [firstpage_image] =>[orig_patent_app_number] => 12587482 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/587482
Interposer structure with passive component and method for fabricating same Oct 5, 2009 Issued
Array ( [id] => 6026948 [patent_doc_number] => 20110079849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-07 [patent_title] => 'LATERAL-DIFFUSION METAL-OXIDE-SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/573892 [patent_app_country] => US [patent_app_date] => 2009-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1593 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20110079849.pdf [firstpage_image] =>[orig_patent_app_number] => 12573892 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/573892
LATERAL-DIFFUSION METAL-OXIDE-SEMICONDUCTOR DEVICE Oct 5, 2009 Abandoned
Array ( [id] => 6508154 [patent_doc_number] => 20100219524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'CHIP SCALE PACKAGE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/574382 [patent_app_country] => US [patent_app_date] => 2009-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3973 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20100219524.pdf [firstpage_image] =>[orig_patent_app_number] => 12574382 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/574382
CHIP SCALE PACKAGE AND METHOD OF FABRICATING THE SAME Oct 5, 2009 Abandoned
Array ( [id] => 9621295 [patent_doc_number] => 08791470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-29 [patent_title] => 'Nano structured LEDs' [patent_app_type] => utility [patent_app_number] => 12/573582 [patent_app_country] => US [patent_app_date] => 2009-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9091 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12573582 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/573582
Nano structured LEDs Oct 4, 2009 Issued
Array ( [id] => 6026931 [patent_doc_number] => 20110079840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-07 [patent_title] => 'MEMORY CELL AND MANUFACTURING METHOD THEREOF AND MEMORY STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/571692 [patent_app_country] => US [patent_app_date] => 2009-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3674 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20110079840.pdf [firstpage_image] =>[orig_patent_app_number] => 12571692 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/571692
MEMORY CELL AND MANUFACTURING METHOD THEREOF AND MEMORY STRUCTURE Sep 30, 2009 Abandoned
Array ( [id] => 6447493 [patent_doc_number] => 20100038710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'Vertical power MOSFET semiconductor apparatus having separate base regions and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/585381 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 11017 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20100038710.pdf [firstpage_image] =>[orig_patent_app_number] => 12585381 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585381
Vertical power MOSFET semiconductor apparatus having separate base regions and manufacturing method thereof Sep 13, 2009 Issued
Array ( [id] => 5483240 [patent_doc_number] => 20090273005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'OPTO-ELECTRONIC PACKAGE STRUCTURE HAVING SILICON-SUBSTRATE AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/499804 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20090273005.pdf [firstpage_image] =>[orig_patent_app_number] => 12499804 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/499804
OPTO-ELECTRONIC PACKAGE STRUCTURE HAVING SILICON-SUBSTRATE AND METHOD OF FORMING THE SAME Jul 8, 2009 Abandoned
Array ( [id] => 6058902 [patent_doc_number] => 20110198719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-18 [patent_title] => 'ELECTRONIC DEVICE COMPRISING A PLURALITY OF ELECTRONIC COMPONENTS LAID DOWN ON A SUBSTRATE AND ASSOCIATED INFRARED SENSOR' [patent_app_type] => utility [patent_app_number] => 12/994597 [patent_app_country] => US [patent_app_date] => 2009-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3087 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20110198719.pdf [firstpage_image] =>[orig_patent_app_number] => 12994597 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/994597
ELECTRONIC DEVICE COMPRISING A PLURALITY OF ELECTRONIC COMPONENTS LAID DOWN ON A SUBSTRATE AND ASSOCIATED INFRARED SENSOR Jul 5, 2009 Abandoned
Array ( [id] => 5495934 [patent_doc_number] => 20090263962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'NON-VOLATILE MEMORY CELL DEVICE AND METHODS' [patent_app_type] => utility [patent_app_number] => 12/496437 [patent_app_country] => US [patent_app_date] => 2009-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20090263962.pdf [firstpage_image] =>[orig_patent_app_number] => 12496437 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/496437
Non-volatile memory cell device and methods Jun 30, 2009 Issued
Array ( [id] => 5483239 [patent_doc_number] => 20090273004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'CHIP PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/485059 [patent_app_country] => US [patent_app_date] => 2009-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9280 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20090273004.pdf [firstpage_image] =>[orig_patent_app_number] => 12485059 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/485059
CHIP PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME Jun 15, 2009 Abandoned
Array ( [id] => 91843 [patent_doc_number] => 07732233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Method for making light emitting diode chip package' [patent_app_type] => utility [patent_app_number] => 12/481578 [patent_app_country] => US [patent_app_date] => 2009-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 5804 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/732/07732233.pdf [firstpage_image] =>[orig_patent_app_number] => 12481578 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/481578
Method for making light emitting diode chip package Jun 9, 2009 Issued
Array ( [id] => 5303215 [patent_doc_number] => 20090297867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'SEMICONDUCTOR THIN FILM-ATTACHED SUBSTRATE AND PRODUCTION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/476440 [patent_app_country] => US [patent_app_date] => 2009-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3438 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0297/20090297867.pdf [firstpage_image] =>[orig_patent_app_number] => 12476440 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/476440
SEMICONDUCTOR THIN FILM-ATTACHED SUBSTRATE AND PRODUCTION METHOD THEREOF Jun 1, 2009 Abandoned
Array ( [id] => 6397193 [patent_doc_number] => 20100304523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'Method of enhancing the conductive and optical properties of deposited indium tin oxide (ITO) thin films' [patent_app_type] => utility [patent_app_number] => 12/457006 [patent_app_country] => US [patent_app_date] => 2009-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0304/20100304523.pdf [firstpage_image] =>[orig_patent_app_number] => 12457006 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/457006
Method of enhancing the conductive and optical properties of deposited indium tin oxide (ITO) thin films May 27, 2009 Issued
Array ( [id] => 6487492 [patent_doc_number] => 20100093165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'Method of fabricating integrated circuit semiconductor device having gate metal silicide layer' [patent_app_type] => utility [patent_app_number] => 12/453866 [patent_app_country] => US [patent_app_date] => 2009-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5854 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20100093165.pdf [firstpage_image] =>[orig_patent_app_number] => 12453866 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/453866
Method of fabricating integrated circuit semiconductor device having gate metal silicide layer May 25, 2009 Abandoned
Array ( [id] => 6460929 [patent_doc_number] => 20100190282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'METHOD FOR MANUFACTURING MULTIPLE-WAVELENGTH SEMICONDUCTOR LASER' [patent_app_type] => utility [patent_app_number] => 12/469755 [patent_app_country] => US [patent_app_date] => 2009-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4194 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20100190282.pdf [firstpage_image] =>[orig_patent_app_number] => 12469755 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/469755
METHOD FOR MANUFACTURING MULTIPLE-WAVELENGTH SEMICONDUCTOR LASER May 20, 2009 Abandoned
Array ( [id] => 6114415 [patent_doc_number] => 20110073946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'LDMOS TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 12/994602 [patent_app_country] => US [patent_app_date] => 2009-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3877 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20110073946.pdf [firstpage_image] =>[orig_patent_app_number] => 12994602 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/994602
LDMOS TRANSISTOR May 18, 2009 Abandoned
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