Robert T. Huber

Array ( [id] => 16386637 [patent_doc_number] => 10811482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Display device including a display module with connecting pins [patent_app_type] => utility [patent_app_number] => 15/796408 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7000 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12650565 [patent_doc_number] => 20180108686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/784398 [patent_app_country] => US [patent_app_date] => 2017-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4496 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15784398 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15358569 [patent_doc_number] => 10527897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Display device with partition between color filters [patent_app_type] => utility [patent_app_number] => 15/784462 [patent_app_country] => US [patent_app_date] => 2017-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 9675 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15784462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15733515 [patent_doc_number] => 10615195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Array substrate with openings in insulation layer for auxiliary elecrode [patent_app_type] => utility [patent_app_number] => 15/784211 [patent_app_country] => US [patent_app_date] => 2017-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 55 [patent_no_of_words] => 11721 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 416 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15784211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12692614 [patent_doc_number] => 20180122704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => DUMMY GATE STRUCTURES AND MANUFACTURING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 15/725223 [patent_app_country] => US [patent_app_date] => 2017-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15725223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14137527 [patent_doc_number] => 20190103153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => 3D CHIP STACK WITH INTEGRATED VOLTAGE REGULATION [patent_app_type] => utility [patent_app_number] => 15/724980 [patent_app_country] => US [patent_app_date] => 2017-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14138323 [patent_doc_number] => 20190103551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => Isolated Hall Effect Element With Improved Electro-Magnetic Isolation [patent_app_type] => utility [patent_app_number] => 15/724576 [patent_app_country] => US [patent_app_date] => 2017-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12896905 [patent_doc_number] => 20180190810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/725091 [patent_app_country] => US [patent_app_date] => 2017-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15725091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14137905 [patent_doc_number] => 20190103342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => SEMICONDUCTOR CHIP PACKAGE COMPRISING SUBSTRATE, SEMICONDUCTOR CHIP, AND LEADFRAME AND A METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/724920 [patent_app_country] => US [patent_app_date] => 2017-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12122469 [patent_doc_number] => 20180006055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/708266 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9678 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15708266 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16249667 [patent_doc_number] => 10749043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Semiconductor device including a trench structure [patent_app_type] => utility [patent_app_number] => 15/704413 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 7503 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12738817 [patent_doc_number] => 20180138106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => Superlattice Structures for Thermoelectric Devices [patent_app_type] => utility [patent_app_number] => 15/700263 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12355080 [patent_doc_number] => 09953872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Semiconductor structure with self-aligned wells and multiple channel materials [patent_app_type] => utility [patent_app_number] => 15/699138 [patent_app_country] => US [patent_app_date] => 2017-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 5673 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15699138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12141133 [patent_doc_number] => 20180019215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/677544 [patent_app_country] => US [patent_app_date] => 2017-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10108 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15677544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12692893 [patent_doc_number] => 20180122797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => FORMING ON-CHIP METAL-INSULATOR-SEMICONDUCTOR CAPACITOR [patent_app_type] => utility [patent_app_number] => 15/668985 [patent_app_country] => US [patent_app_date] => 2017-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15668985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15488385 [patent_doc_number] => 10559554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Method for fabricating LED module using transfer tape [patent_app_type] => utility [patent_app_number] => 15/558192 [patent_app_country] => US [patent_app_date] => 2017-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 11674 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15558192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11990146 [patent_doc_number] => 20170294301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'METHOD OF GROWING A HIGH QUALITY III-V COMPOUND LAYER ON A SILICON SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 15/632920 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7117 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15632920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16645580 [patent_doc_number] => 10923448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Bond pad with micro-protrusions for direct metallic bonding [patent_app_type] => utility [patent_app_number] => 15/627314 [patent_app_country] => US [patent_app_date] => 2017-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 4840 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15704027 [patent_doc_number] => 10608202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Display apparatus with bent area including spaced patterns [patent_app_type] => utility [patent_app_number] => 15/591563 [patent_app_country] => US [patent_app_date] => 2017-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7174 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15591563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11939801 [patent_doc_number] => 20170243951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'POWER DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/588270 [patent_app_country] => US [patent_app_date] => 2017-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15588270 [rel_patent_id] =>[rel_patent_doc_number] =>)