Robert Thomas Crow

Array ( [id] => 19459965 [patent_doc_number] => 12100467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Systems and methods for testing redundant fuse latches in a memory device [patent_app_type] => utility [patent_app_number] => 17/822032 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5252 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17822032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18990863 [patent_doc_number] => 20240062832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => 3D NAND MEMORY WITH FAST CORRECTIVE READ [patent_app_type] => utility [patent_app_number] => 17/891544 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18781983 [patent_doc_number] => 11823748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Voltage bin calibration based on a temporary voltage shift offset [patent_app_type] => utility [patent_app_number] => 17/820792 [patent_app_country] => US [patent_app_date] => 2022-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 16478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17820792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18431437 [patent_doc_number] => 11676664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Voltage bin selection for blocks of a memory device after power up of the memory device [patent_app_type] => utility [patent_app_number] => 17/883538 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18408673 [patent_doc_number] => 20230170026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => METHOD AND APPARATUS WITH MEMORY ARRAY PROGRAMING [patent_app_type] => utility [patent_app_number] => 17/880849 [patent_app_country] => US [patent_app_date] => 2022-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17880849 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19356710 [patent_doc_number] => 12057165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Method of programming a select transistor of a semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/879975 [patent_app_country] => US [patent_app_date] => 2022-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 34 [patent_no_of_words] => 12630 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18958670 [patent_doc_number] => 20240046997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => NON-VOLATILE MEMORY DEVICE FOR MITIGATING CYCLING TRAPPED EFFECT AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/878933 [patent_app_country] => US [patent_app_date] => 2022-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17878933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18548051 [patent_doc_number] => 11721409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Smart sampling for block family scan [patent_app_type] => utility [patent_app_number] => 17/877810 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 22769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19494110 [patent_doc_number] => 12112831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Memory row-hammer mitigation [patent_app_type] => utility [patent_app_number] => 17/877592 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15864 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18639272 [patent_doc_number] => 11763888 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-19 [patent_title] => Range segmenting for analog CAM with improved precision [patent_app_type] => utility [patent_app_number] => 17/872923 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17985745 [patent_doc_number] => 20220351782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => MULTI-STAGE ERASE OPERATION FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/868703 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17963403 [patent_doc_number] => 20220343984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => VALID TRANSLATION UNIT COUNT-BASED MEMORY MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/859926 [patent_app_country] => US [patent_app_date] => 2022-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17859926 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18500313 [patent_doc_number] => 20230223098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => METHOD AND DEVICE FOR TESTING MEMORY [patent_app_type] => utility [patent_app_number] => 17/857235 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17949003 [patent_doc_number] => 20220336022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => ANALOG PEAK POWER MANAGEMENT FOR MULTI-DIE OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/857674 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857674 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18097064 [patent_doc_number] => 20220415405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => MEMORY-CONTROL CIRCUIT AND METHOD FOR CONTROLLING ERASING OPERATION OF FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 17/852597 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17932982 [patent_doc_number] => 20220328108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => ANALOG PEAK POWER MANAGEMENT FOR MULTI-DIE OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/852649 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -38 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18270639 [patent_doc_number] => 20230091881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => KEY STORAGE DEVICE AND KEY GENERATION METHOD [patent_app_type] => utility [patent_app_number] => 17/848409 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18865587 [patent_doc_number] => 20230420024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => ADJUSTING REFRESH RATE DURING SELF-REFRESH STATE [patent_app_type] => utility [patent_app_number] => 17/849100 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19567542 [patent_doc_number] => 12142319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Hybrid type content addressable memory for implementing in-memory-search and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/846304 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 7728 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18061423 [patent_doc_number] => 20220392509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => MEMORY ACCESSING WITH AUTO-PRECHARGE [patent_app_type] => utility [patent_app_number] => 17/846751 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846751 [rel_patent_id] =>[rel_patent_doc_number] =>)