| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2678887
[patent_doc_number] => 04999837
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-03-12
[patent_title] => 'Programmable channel error injection'
[patent_app_type] => 1
[patent_app_number] => 7/325417
[patent_app_country] => US
[patent_app_date] => 1989-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4244
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/999/04999837.pdf
[firstpage_image] =>[orig_patent_app_number] => 325417
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/325417 | Programmable channel error injection | Mar 19, 1989 | Issued |
Array
(
[id] => 2716836
[patent_doc_number] => 04993029
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-02-12
[patent_title] => 'Method and apparatus for randomizing data in a direct access storage device'
[patent_app_type] => 1
[patent_app_number] => 7/322588
[patent_app_country] => US
[patent_app_date] => 1989-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 7382
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/993/04993029.pdf
[firstpage_image] =>[orig_patent_app_number] => 322588
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/322588 | Method and apparatus for randomizing data in a direct access storage device | Mar 12, 1989 | Issued |
Array
(
[id] => 2744795
[patent_doc_number] => 05051999
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-24
[patent_title] => 'Programmable error correcting apparatus within a paging receiver'
[patent_app_type] => 1
[patent_app_number] => 7/322437
[patent_app_country] => US
[patent_app_date] => 1989-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 10573
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/051/05051999.pdf
[firstpage_image] =>[orig_patent_app_number] => 322437
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/322437 | Programmable error correcting apparatus within a paging receiver | Mar 12, 1989 | Issued |
| 07/321827 | FAULT TOLERANT COMPUTER MEMORY SYSTEMS AND COMPONENTS EMPLOYING DUAL LEVEL ERROR CORRECTION AND DETECTION WITH DISABLEMENT FEATURE | Mar 9, 1989 | Abandoned |
Array
(
[id] => 2599074
[patent_doc_number] => 04959833
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-25
[patent_title] => 'Data transmission method and bus extender'
[patent_app_type] => 1
[patent_app_number] => 7/321528
[patent_app_country] => US
[patent_app_date] => 1989-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 5822
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/959/04959833.pdf
[firstpage_image] =>[orig_patent_app_number] => 321528
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/321528 | Data transmission method and bus extender | Mar 7, 1989 | Issued |
Array
(
[id] => 2627186
[patent_doc_number] => 04969148
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-11-06
[patent_title] => 'Serial testing technique for embedded memories'
[patent_app_type] => 1
[patent_app_number] => 7/319979
[patent_app_country] => US
[patent_app_date] => 1989-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5265
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 739
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/969/04969148.pdf
[firstpage_image] =>[orig_patent_app_number] => 319979
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/319979 | Serial testing technique for embedded memories | Mar 6, 1989 | Issued |
Array
(
[id] => 2677277
[patent_doc_number] => 05070503
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-03
[patent_title] => 'Digital information transmitting and receiving system'
[patent_app_type] => 1
[patent_app_number] => 7/320089
[patent_app_country] => US
[patent_app_date] => 1989-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 5159
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/070/05070503.pdf
[firstpage_image] =>[orig_patent_app_number] => 320089
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/320089 | Digital information transmitting and receiving system | Mar 6, 1989 | Issued |
Array
(
[id] => 2720341
[patent_doc_number] => 05018148
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-21
[patent_title] => 'Method and apparatus for power failure protection'
[patent_app_type] => 1
[patent_app_number] => 7/317384
[patent_app_country] => US
[patent_app_date] => 1989-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3240
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/018/05018148.pdf
[firstpage_image] =>[orig_patent_app_number] => 317384
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/317384 | Method and apparatus for power failure protection | Feb 28, 1989 | Issued |
Array
(
[id] => 2851844
[patent_doc_number] => 05172379
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-15
[patent_title] => 'High performance memory system'
[patent_app_type] => 1
[patent_app_number] => 7/315394
[patent_app_country] => US
[patent_app_date] => 1989-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3702
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/172/05172379.pdf
[firstpage_image] =>[orig_patent_app_number] => 315394
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/315394 | High performance memory system | Feb 23, 1989 | Issued |
Array
(
[id] => 2755488
[patent_doc_number] => 05023874
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-06-11
[patent_title] => 'Screening logic circuits for preferred states'
[patent_app_type] => 1
[patent_app_number] => 7/314619
[patent_app_country] => US
[patent_app_date] => 1989-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2046
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/023/05023874.pdf
[firstpage_image] =>[orig_patent_app_number] => 314619
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/314619 | Screening logic circuits for preferred states | Feb 22, 1989 | Issued |
Array
(
[id] => 2760348
[patent_doc_number] => 05022029
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-06-04
[patent_title] => 'Data transmission method and device'
[patent_app_type] => 1
[patent_app_number] => 7/312007
[patent_app_country] => US
[patent_app_date] => 1989-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 5384
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/022/05022029.pdf
[firstpage_image] =>[orig_patent_app_number] => 312007
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/312007 | Data transmission method and device | Feb 16, 1989 | Issued |
| 07/311695 | VERY HIGH SPEED ERROR DETECTION NETWORK | Feb 15, 1989 | Abandoned |
Array
(
[id] => 2776889
[patent_doc_number] => 05036516
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-30
[patent_title] => 'Process and means for selftest of RAMs in an electronic device'
[patent_app_type] => 1
[patent_app_number] => 7/309138
[patent_app_country] => US
[patent_app_date] => 1989-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2093
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/036/05036516.pdf
[firstpage_image] =>[orig_patent_app_number] => 309138
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/309138 | Process and means for selftest of RAMs in an electronic device | Feb 12, 1989 | Issued |
Array
(
[id] => 2599095
[patent_doc_number] => 04959834
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-25
[patent_title] => 'Word syncronization system and method'
[patent_app_type] => 1
[patent_app_number] => 7/309587
[patent_app_country] => US
[patent_app_date] => 1989-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 5214
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 22
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/959/04959834.pdf
[firstpage_image] =>[orig_patent_app_number] => 309587
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/309587 | Word syncronization system and method | Feb 12, 1989 | Issued |
Array
(
[id] => 2525512
[patent_doc_number] => 04875212
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-17
[patent_title] => 'Memory device with integrated error detection and correction'
[patent_app_type] => 1
[patent_app_number] => 7/310496
[patent_app_country] => US
[patent_app_date] => 1989-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 4618
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/875/04875212.pdf
[firstpage_image] =>[orig_patent_app_number] => 310496
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/310496 | Memory device with integrated error detection and correction | Feb 12, 1989 | Issued |
Array
(
[id] => 2755674
[patent_doc_number] => 05003541
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-03-26
[patent_title] => 'Method and circuit for semiconductor memory processing of video signals with Reed-Solomon error detection'
[patent_app_type] => 1
[patent_app_number] => 7/309697
[patent_app_country] => US
[patent_app_date] => 1989-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 4143
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/003/05003541.pdf
[firstpage_image] =>[orig_patent_app_number] => 309697
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/309697 | Method and circuit for semiconductor memory processing of video signals with Reed-Solomon error detection | Feb 9, 1989 | Issued |
Array
(
[id] => 2672964
[patent_doc_number] => 04947395
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-08-07
[patent_title] => 'Bus executed scan testing method and apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/308917
[patent_app_country] => US
[patent_app_date] => 1989-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5652
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/947/04947395.pdf
[firstpage_image] =>[orig_patent_app_number] => 308917
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/308917 | Bus executed scan testing method and apparatus | Feb 9, 1989 | Issued |
| 07/327958 | PROCESS FOR THE LOCALISATION OF DEFECTIVE STATIONS IN LOCAL NETWORKS AND ASSOCIATED INTERFACE CONTROLLER | Feb 9, 1989 | Abandoned |
Array
(
[id] => 2759135
[patent_doc_number] => 05031176
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-09
[patent_title] => 'Connection interface of an information receiving part of a station in a differential information transmission system through two transmission lines, in particular in an automobile vehicle'
[patent_app_type] => 1
[patent_app_number] => 7/308028
[patent_app_country] => US
[patent_app_date] => 1989-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2242
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 357
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/031/05031176.pdf
[firstpage_image] =>[orig_patent_app_number] => 308028
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/308028 | Connection interface of an information receiving part of a station in a differential information transmission system through two transmission lines, in particular in an automobile vehicle | Feb 8, 1989 | Issued |
| 07/307170 | CONVOLUTIONAL ENCODER AND SEQUENTIAL DECODER WITH PARALLEL ARCHITECTURE AND BLOCK CODING PROPERTIES | Feb 5, 1989 | Abandoned |