
Robert W. Beausoliel Jr.
Examiner (ID: 5619)
| Most Active Art Unit | 2306 |
| Art Unit(s) | 2184, 2306, 2785, 2113, 2313, 2167, 2413 |
| Total Applications | 522 |
| Issued Applications | 450 |
| Pending Applications | 14 |
| Abandoned Applications | 60 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2717646
[patent_doc_number] => 04982402
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-01
[patent_title] => 'Method and apparatus for detecting and correcting errors in a pipelined computer system'
[patent_app_type] => 1
[patent_app_number] => 7/306828
[patent_app_country] => US
[patent_app_date] => 1989-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8199
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/982/04982402.pdf
[firstpage_image] =>[orig_patent_app_number] => 306828
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/306828 | Method and apparatus for detecting and correcting errors in a pipelined computer system | Feb 2, 1989 | Issued |
Array
(
[id] => 2722712
[patent_doc_number] => 05010550
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-04-23
[patent_title] => 'Transmission line switching system'
[patent_app_type] => 1
[patent_app_number] => 7/305927
[patent_app_country] => US
[patent_app_date] => 1989-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3720
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/010/05010550.pdf
[firstpage_image] =>[orig_patent_app_number] => 305927
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/305927 | Transmission line switching system | Feb 1, 1989 | Issued |
Array
(
[id] => 2703611
[patent_doc_number] => 04996689
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-02-26
[patent_title] => 'Method of generating tests for a combinational logic circuit'
[patent_app_type] => 1
[patent_app_number] => 7/305449
[patent_app_country] => US
[patent_app_date] => 1989-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2808
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/996/04996689.pdf
[firstpage_image] =>[orig_patent_app_number] => 305449
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/305449 | Method of generating tests for a combinational logic circuit | Jan 31, 1989 | Issued |
Array
(
[id] => 2717513
[patent_doc_number] => 05014273
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-07
[patent_title] => 'Bad data algorithm'
[patent_app_type] => 1
[patent_app_number] => 7/303574
[patent_app_country] => US
[patent_app_date] => 1989-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2230
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 273
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/014/05014273.pdf
[firstpage_image] =>[orig_patent_app_number] => 303574
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/303574 | Bad data algorithm | Jan 26, 1989 | Issued |
Array
(
[id] => 2683415
[patent_doc_number] => 04984241
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-08
[patent_title] => 'Tightly synchronized fault tolerant clock'
[patent_app_type] => 1
[patent_app_number] => 7/301327
[patent_app_country] => US
[patent_app_date] => 1989-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3985
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/984/04984241.pdf
[firstpage_image] =>[orig_patent_app_number] => 301327
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/301327 | Tightly synchronized fault tolerant clock | Jan 22, 1989 | Issued |
Array
(
[id] => 2613768
[patent_doc_number] => 04949343
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-08-14
[patent_title] => 'Error detecting circuit for a decoder'
[patent_app_type] => 1
[patent_app_number] => 7/298369
[patent_app_country] => US
[patent_app_date] => 1989-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 4197
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/949/04949343.pdf
[firstpage_image] =>[orig_patent_app_number] => 298369
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/298369 | Error detecting circuit for a decoder | Jan 17, 1989 | Issued |
Array
(
[id] => 2773881
[patent_doc_number] => 04995042
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-02-19
[patent_title] => 'Switching exchange'
[patent_app_type] => 1
[patent_app_number] => 7/296269
[patent_app_country] => US
[patent_app_date] => 1989-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2523
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/995/04995042.pdf
[firstpage_image] =>[orig_patent_app_number] => 296269
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/296269 | Switching exchange | Jan 8, 1989 | Issued |
Array
(
[id] => 2640987
[patent_doc_number] => 04958346
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-18
[patent_title] => 'Memory testing device'
[patent_app_type] => 1
[patent_app_number] => 7/292100
[patent_app_country] => US
[patent_app_date] => 1988-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3565
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 545
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/958/04958346.pdf
[firstpage_image] =>[orig_patent_app_number] => 292100
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/292100 | Memory testing device | Dec 29, 1988 | Issued |
Array
(
[id] => 2656101
[patent_doc_number] => 04980889
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-12-25
[patent_title] => 'Multi-mode testing systems'
[patent_app_type] => 1
[patent_app_number] => 7/291727
[patent_app_country] => US
[patent_app_date] => 1988-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 4364
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/980/04980889.pdf
[firstpage_image] =>[orig_patent_app_number] => 291727
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/291727 | Multi-mode testing systems | Dec 28, 1988 | Issued |
Array
(
[id] => 2776337
[patent_doc_number] => 05007054
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-04-09
[patent_title] => 'Network and protocol for real-time control of machine operations'
[patent_app_type] => 1
[patent_app_number] => 7/291477
[patent_app_country] => US
[patent_app_date] => 1988-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 43
[patent_figures_cnt] => 47
[patent_no_of_words] => 16746
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 415
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/007/05007054.pdf
[firstpage_image] =>[orig_patent_app_number] => 291477
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/291477 | Network and protocol for real-time control of machine operations | Dec 27, 1988 | Issued |
Array
(
[id] => 2742979
[patent_doc_number] => 05040180
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-13
[patent_title] => 'Method and device for securing data'
[patent_app_type] => 1
[patent_app_number] => 7/290035
[patent_app_country] => US
[patent_app_date] => 1988-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1470
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/040/05040180.pdf
[firstpage_image] =>[orig_patent_app_number] => 290035
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/290035 | Method and device for securing data | Dec 26, 1988 | Issued |
Array
(
[id] => 2776370
[patent_doc_number] => 05007056
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-04-09
[patent_title] => 'Processing circuit having an error detecting and correcting circuit therein'
[patent_app_type] => 1
[patent_app_number] => 7/289708
[patent_app_country] => US
[patent_app_date] => 1988-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1810
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/007/05007056.pdf
[firstpage_image] =>[orig_patent_app_number] => 289708
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/289708 | Processing circuit having an error detecting and correcting circuit therein | Dec 26, 1988 | Issued |
Array
(
[id] => 2598200
[patent_doc_number] => 04964124
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-10-16
[patent_title] => 'Computer peripheral tester'
[patent_app_type] => 1
[patent_app_number] => 7/291108
[patent_app_country] => US
[patent_app_date] => 1988-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6546
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/964/04964124.pdf
[firstpage_image] =>[orig_patent_app_number] => 291108
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/291108 | Computer peripheral tester | Dec 26, 1988 | Issued |
| 07/289126 | SINGLE-ERROR DETECTING AND CORRECTING SYSTEM | Dec 22, 1988 | Abandoned |
Array
(
[id] => 2756063
[patent_doc_number] => 05012472
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-04-30
[patent_title] => 'Dynamic type semiconductor memory device having an error checking and correcting circuit'
[patent_app_type] => 1
[patent_app_number] => 7/288218
[patent_app_country] => US
[patent_app_date] => 1988-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5266
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/012/05012472.pdf
[firstpage_image] =>[orig_patent_app_number] => 288218
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/288218 | Dynamic type semiconductor memory device having an error checking and correcting circuit | Dec 21, 1988 | Issued |
Array
(
[id] => 2683385
[patent_doc_number] => 04984240
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-08
[patent_title] => 'Distributed switching architecture for communication module redundancy'
[patent_app_type] => 1
[patent_app_number] => 7/288788
[patent_app_country] => US
[patent_app_date] => 1988-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4046
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/984/04984240.pdf
[firstpage_image] =>[orig_patent_app_number] => 288788
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/288788 | Distributed switching architecture for communication module redundancy | Dec 21, 1988 | Issued |
Array
(
[id] => 2598291
[patent_doc_number] => 04964129
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-10-16
[patent_title] => 'Memory controller with error logging'
[patent_app_type] => 1
[patent_app_number] => 7/287927
[patent_app_country] => US
[patent_app_date] => 1988-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 4323
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/964/04964129.pdf
[firstpage_image] =>[orig_patent_app_number] => 287927
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/287927 | Memory controller with error logging | Dec 20, 1988 | Issued |
Array
(
[id] => 2640969
[patent_doc_number] => 04958345
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-18
[patent_title] => 'Memory testing device'
[patent_app_type] => 1
[patent_app_number] => 7/287139
[patent_app_country] => US
[patent_app_date] => 1988-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 7987
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 269
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/958/04958345.pdf
[firstpage_image] =>[orig_patent_app_number] => 287139
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/287139 | Memory testing device | Dec 20, 1988 | Issued |
Array
(
[id] => 2598311
[patent_doc_number] => 04964130
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-10-16
[patent_title] => 'System for determining status of errors in a memory subsystem'
[patent_app_type] => 1
[patent_app_number] => 7/287928
[patent_app_country] => US
[patent_app_date] => 1988-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4088
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/964/04964130.pdf
[firstpage_image] =>[orig_patent_app_number] => 287928
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/287928 | System for determining status of errors in a memory subsystem | Dec 20, 1988 | Issued |
Array
(
[id] => 2757674
[patent_doc_number] => 05016249
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-14
[patent_title] => 'Dual computer cross-checking system'
[patent_app_type] => 1
[patent_app_number] => 7/286154
[patent_app_country] => US
[patent_app_date] => 1988-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4361
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/016/05016249.pdf
[firstpage_image] =>[orig_patent_app_number] => 286154
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/286154 | Dual computer cross-checking system | Dec 18, 1988 | Issued |