
Robert W. Beausoliel Jr.
Examiner (ID: 5619)
| Most Active Art Unit | 2306 |
| Art Unit(s) | 2184, 2306, 2785, 2113, 2313, 2167, 2413 |
| Total Applications | 522 |
| Issued Applications | 450 |
| Pending Applications | 14 |
| Abandoned Applications | 60 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2742762
[patent_doc_number] => 04998251
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-03-05
[patent_title] => 'Method of detecting erasures affecting a digital radio link and a receiver system implementing such a method'
[patent_app_type] => 1
[patent_app_number] => 7/286439
[patent_app_country] => US
[patent_app_date] => 1988-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2675
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/998/04998251.pdf
[firstpage_image] =>[orig_patent_app_number] => 286439
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/286439 | Method of detecting erasures affecting a digital radio link and a receiver system implementing such a method | Dec 15, 1988 | Issued |
Array
(
[id] => 2637040
[patent_doc_number] => 04951284
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-08-21
[patent_title] => 'Method and means for correcting random and burst errors'
[patent_app_type] => 1
[patent_app_number] => 7/284979
[patent_app_country] => US
[patent_app_date] => 1988-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 7034
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/951/04951284.pdf
[firstpage_image] =>[orig_patent_app_number] => 284979
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/284979 | Method and means for correcting random and burst errors | Dec 13, 1988 | Issued |
Array
(
[id] => 2779679
[patent_doc_number] => 04985894
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-15
[patent_title] => 'Fault information collection processing system'
[patent_app_type] => 1
[patent_app_number] => 7/284078
[patent_app_country] => US
[patent_app_date] => 1988-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4850
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/985/04985894.pdf
[firstpage_image] =>[orig_patent_app_number] => 284078
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/284078 | Fault information collection processing system | Dec 13, 1988 | Issued |
Array
(
[id] => 2599056
[patent_doc_number] => 04959832
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-25
[patent_title] => 'Parallel pseudorandom pattern generator with varying phase shift'
[patent_app_type] => 1
[patent_app_number] => 7/281617
[patent_app_country] => US
[patent_app_date] => 1988-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4829
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/959/04959832.pdf
[firstpage_image] =>[orig_patent_app_number] => 281617
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/281617 | Parallel pseudorandom pattern generator with varying phase shift | Dec 8, 1988 | Issued |
Array
(
[id] => 2484876
[patent_doc_number] => 04872169
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-03
[patent_title] => 'Hierarchical scan selection'
[patent_app_type] => 1
[patent_app_number] => 7/282827
[patent_app_country] => US
[patent_app_date] => 1988-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 4423
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/872/04872169.pdf
[firstpage_image] =>[orig_patent_app_number] => 282827
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/282827 | Hierarchical scan selection | Dec 7, 1988 | Issued |
Array
(
[id] => 2689248
[patent_doc_number] => 05005173
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-04-02
[patent_title] => 'Parallel module testing'
[patent_app_type] => 1
[patent_app_number] => 7/281308
[patent_app_country] => US
[patent_app_date] => 1988-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3533
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/005/05005173.pdf
[firstpage_image] =>[orig_patent_app_number] => 281308
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/281308 | Parallel module testing | Dec 6, 1988 | Issued |
| 07/276499 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH A SELF-TEST FUNCTION | Nov 22, 1988 | Abandoned |
Array
(
[id] => 2604774
[patent_doc_number] => 04933939
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-06-12
[patent_title] => 'Method and apparatus for error measurement and reduction in a mass storage device memory system'
[patent_app_type] => 1
[patent_app_number] => 7/276209
[patent_app_country] => US
[patent_app_date] => 1988-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 18
[patent_no_of_words] => 8225
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/933/04933939.pdf
[firstpage_image] =>[orig_patent_app_number] => 276209
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/276209 | Method and apparatus for error measurement and reduction in a mass storage device memory system | Nov 22, 1988 | Issued |
Array
(
[id] => 2633961
[patent_doc_number] => 04956842
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-11
[patent_title] => 'Diagnostic system for a watchdog timer'
[patent_app_type] => 1
[patent_app_number] => 7/272059
[patent_app_country] => US
[patent_app_date] => 1988-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5123
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/956/04956842.pdf
[firstpage_image] =>[orig_patent_app_number] => 272059
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/272059 | Diagnostic system for a watchdog timer | Nov 15, 1988 | Issued |
Array
(
[id] => 2607740
[patent_doc_number] => 04924468
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-05-08
[patent_title] => 'Logic analyzer'
[patent_app_type] => 1
[patent_app_number] => 7/272158
[patent_app_country] => US
[patent_app_date] => 1988-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 4934
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 329
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/924/04924468.pdf
[firstpage_image] =>[orig_patent_app_number] => 272158
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/272158 | Logic analyzer | Nov 15, 1988 | Issued |
Array
(
[id] => 2626899
[patent_doc_number] => 04913557
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-04-03
[patent_title] => 'Intergrated logic circuit having testing function circuit formed integrally therewith'
[patent_app_type] => 1
[patent_app_number] => 7/271488
[patent_app_country] => US
[patent_app_date] => 1988-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6598
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/913/04913557.pdf
[firstpage_image] =>[orig_patent_app_number] => 271488
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/271488 | Intergrated logic circuit having testing function circuit formed integrally therewith | Nov 14, 1988 | Issued |
Array
(
[id] => 2647124
[patent_doc_number] => 04910734
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-03-20
[patent_title] => 'Intergrated circuit having testing function circuit and control circuit therefor'
[patent_app_type] => 1
[patent_app_number] => 7/271487
[patent_app_country] => US
[patent_app_date] => 1988-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6951
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/910/04910734.pdf
[firstpage_image] =>[orig_patent_app_number] => 271487
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/271487 | Intergrated circuit having testing function circuit and control circuit therefor | Nov 14, 1988 | Issued |
Array
(
[id] => 2600114
[patent_doc_number] => RE033332
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-11
[patent_title] => 'Apparatus for correcting errors'
[patent_app_type] => 2
[patent_app_number] => 7/270051
[patent_app_country] => US
[patent_app_date] => 1988-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 26
[patent_no_of_words] => 8549
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 269
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/033/RE033332.pdf
[firstpage_image] =>[orig_patent_app_number] => 270051
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/270051 | Apparatus for correcting errors | Nov 13, 1988 | Issued |
Array
(
[id] => 2565549
[patent_doc_number] => 04961191
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-10-02
[patent_title] => 'Test circuit for logic circuits'
[patent_app_type] => 1
[patent_app_number] => 7/269507
[patent_app_country] => US
[patent_app_date] => 1988-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3302
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/961/04961191.pdf
[firstpage_image] =>[orig_patent_app_number] => 269507
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/269507 | Test circuit for logic circuits | Nov 9, 1988 | Issued |
Array
(
[id] => 2665588
[patent_doc_number] => 04972416
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-11-20
[patent_title] => 'Error detection and correction method'
[patent_app_type] => 1
[patent_app_number] => 7/268778
[patent_app_country] => US
[patent_app_date] => 1988-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4045
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/972/04972416.pdf
[firstpage_image] =>[orig_patent_app_number] => 268778
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/268778 | Error detection and correction method | Nov 8, 1988 | Issued |
Array
(
[id] => 2599319
[patent_doc_number] => 04970727
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-11-13
[patent_title] => 'Semiconductor integrated circuit having multiple self-test functions and operating method therefor'
[patent_app_type] => 1
[patent_app_number] => 7/263118
[patent_app_country] => US
[patent_app_date] => 1988-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 4812
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/970/04970727.pdf
[firstpage_image] =>[orig_patent_app_number] => 263118
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/263118 | Semiconductor integrated circuit having multiple self-test functions and operating method therefor | Oct 26, 1988 | Issued |
Array
(
[id] => 2772968
[patent_doc_number] => 04994993
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-02-19
[patent_title] => 'System for detecting and correcting errors generated by arithmetic logic units'
[patent_app_type] => 1
[patent_app_number] => 7/262658
[patent_app_country] => US
[patent_app_date] => 1988-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5143
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 417
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/994/04994993.pdf
[firstpage_image] =>[orig_patent_app_number] => 262658
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/262658 | System for detecting and correcting errors generated by arithmetic logic units | Oct 24, 1988 | Issued |
| 07/255658 | FAULT DIAGNOSING AND IDENTIFICATION SYSTEM FOR REPRODUCTION MACHINES | Oct 12, 1988 | Abandoned |
Array
(
[id] => 2678972
[patent_doc_number] => 04955022
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-04
[patent_title] => 'Encoding apparatus and method for error correction'
[patent_app_type] => 1
[patent_app_number] => 7/252807
[patent_app_country] => US
[patent_app_date] => 1988-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 20
[patent_no_of_words] => 4610
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/955/04955022.pdf
[firstpage_image] =>[orig_patent_app_number] => 252807
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/252807 | Encoding apparatus and method for error correction | Sep 29, 1988 | Issued |
Array
(
[id] => 2756045
[patent_doc_number] => 05012471
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-04-30
[patent_title] => 'Value-strength based test pattern generator and process'
[patent_app_type] => 1
[patent_app_number] => 7/252289
[patent_app_country] => US
[patent_app_date] => 1988-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 15569
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/012/05012471.pdf
[firstpage_image] =>[orig_patent_app_number] => 252289
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/252289 | Value-strength based test pattern generator and process | Sep 29, 1988 | Issued |