Search

Robert W. Beausoliel Jr.

Examiner (ID: 5619)

Most Active Art Unit
2306
Art Unit(s)
2184, 2306, 2785, 2113, 2313, 2167, 2413
Total Applications
522
Issued Applications
450
Pending Applications
14
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2495785 [patent_doc_number] => 04866717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-12 [patent_title] => 'Code error detecting and correcting apparatus' [patent_app_type] => 1 [patent_app_number] => 7/077608 [patent_app_country] => US [patent_app_date] => 1987-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5356 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/866/04866717.pdf [firstpage_image] =>[orig_patent_app_number] => 077608 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/077608
Code error detecting and correcting apparatus Jul 23, 1987 Issued
07/074848 IN OR RELATING TO SIGNATURE ANALYSIS Jul 16, 1987 Abandoned
07/072639 CONVOLUTIONAL ENCODER AND SEQUENTIAL DECODER WITH PARALLEL ARCHITECTURE AND BLOCK CODING PROPERTIES Jul 12, 1987 Abandoned
Array ( [id] => 2570774 [patent_doc_number] => 04837765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-06-06 [patent_title] => 'Test control circuit for integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/071068 [patent_app_country] => US [patent_app_date] => 1987-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3508 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/837/04837765.pdf [firstpage_image] =>[orig_patent_app_number] => 071068 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/071068
Test control circuit for integrated circuit Jul 7, 1987 Issued
Array ( [id] => 2423290 [patent_doc_number] => 04744084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-10 [patent_title] => 'Hardware modeling system and method for simulating portions of electrical circuits' [patent_app_type] => 1 [patent_app_number] => 7/070598 [patent_app_country] => US [patent_app_date] => 1987-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 16303 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/744/04744084.pdf [firstpage_image] =>[orig_patent_app_number] => 070598 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/070598
Hardware modeling system and method for simulating portions of electrical circuits Jul 7, 1987 Issued
Array ( [id] => 2568541 [patent_doc_number] => 04817093 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-28 [patent_title] => 'Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure' [patent_app_type] => 1 [patent_app_number] => 7/064976 [patent_app_country] => US [patent_app_date] => 1987-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 9037 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/817/04817093.pdf [firstpage_image] =>[orig_patent_app_number] => 064976 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/064976
Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure Jun 17, 1987 Issued
Array ( [id] => 2678804 [patent_doc_number] => 04905242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-27 [patent_title] => 'Pipelined error detection and correction apparatus with programmable address trap' [patent_app_type] => 1 [patent_app_number] => 7/059696 [patent_app_country] => US [patent_app_date] => 1987-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2971 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/905/04905242.pdf [firstpage_image] =>[orig_patent_app_number] => 059696 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/059696
Pipelined error detection and correction apparatus with programmable address trap Jun 8, 1987 Issued
Array ( [id] => 2499448 [patent_doc_number] => 04868817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-19 [patent_title] => 'Circuit for preventing a microcomputer from malfunctioning' [patent_app_type] => 1 [patent_app_number] => 7/058269 [patent_app_country] => US [patent_app_date] => 1987-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4287 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/868/04868817.pdf [firstpage_image] =>[orig_patent_app_number] => 058269 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/058269
Circuit for preventing a microcomputer from malfunctioning Jun 3, 1987 Issued
Array ( [id] => 2501545 [patent_doc_number] => 04860290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-22 [patent_title] => 'Logic circuit having individually testable logic modules' [patent_app_type] => 1 [patent_app_number] => 7/057078 [patent_app_country] => US [patent_app_date] => 1987-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11712 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/860/04860290.pdf [firstpage_image] =>[orig_patent_app_number] => 057078 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/057078
Logic circuit having individually testable logic modules Jun 1, 1987 Issued
Array ( [id] => 2398398 [patent_doc_number] => 04794602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-27 [patent_title] => 'Method for error detection' [patent_app_type] => 1 [patent_app_number] => 7/054426 [patent_app_country] => US [patent_app_date] => 1987-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3251 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/794/04794602.pdf [firstpage_image] =>[orig_patent_app_number] => 054426 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/054426
Method for error detection May 25, 1987 Issued
Array ( [id] => 2573427 [patent_doc_number] => 04835774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-30 [patent_title] => 'Semiconductor memory test system' [patent_app_type] => 1 [patent_app_number] => 7/051399 [patent_app_country] => US [patent_app_date] => 1987-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4181 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/835/04835774.pdf [firstpage_image] =>[orig_patent_app_number] => 051399 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/051399
Semiconductor memory test system May 18, 1987 Issued
Array ( [id] => 2579587 [patent_doc_number] => 04901316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-13 [patent_title] => 'Disaster prevention monitoring and control facility' [patent_app_type] => 1 [patent_app_number] => 7/050476 [patent_app_country] => US [patent_app_date] => 1987-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5621 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/901/04901316.pdf [firstpage_image] =>[orig_patent_app_number] => 050476 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/050476
Disaster prevention monitoring and control facility May 17, 1987 Issued
Array ( [id] => 2491859 [patent_doc_number] => 04823347 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-18 [patent_title] => 'Deferred parity checking of control signals across a bidirectional data transmission interface' [patent_app_type] => 1 [patent_app_number] => 7/050778 [patent_app_country] => US [patent_app_date] => 1987-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5437 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/823/04823347.pdf [firstpage_image] =>[orig_patent_app_number] => 050778 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/050778
Deferred parity checking of control signals across a bidirectional data transmission interface May 17, 1987 Issued
Array ( [id] => 2562860 [patent_doc_number] => 04807229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-02-21 [patent_title] => 'Semiconductor device tester' [patent_app_type] => 1 [patent_app_number] => 7/050549 [patent_app_country] => US [patent_app_date] => 1987-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3120 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/807/04807229.pdf [firstpage_image] =>[orig_patent_app_number] => 050549 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/050549
Semiconductor device tester May 17, 1987 Issued
Array ( [id] => 2568583 [patent_doc_number] => 04817095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-28 [patent_title] => 'Byte write error code method and apparatus' [patent_app_type] => 1 [patent_app_number] => 7/050839 [patent_app_country] => US [patent_app_date] => 1987-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5765 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/817/04817095.pdf [firstpage_image] =>[orig_patent_app_number] => 050839 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/050839
Byte write error code method and apparatus May 14, 1987 Issued
Array ( [id] => 2552918 [patent_doc_number] => 04827477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-02 [patent_title] => 'Bus interface unit' [patent_app_type] => 1 [patent_app_number] => 7/050758 [patent_app_country] => US [patent_app_date] => 1987-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 9187 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/827/04827477.pdf [firstpage_image] =>[orig_patent_app_number] => 050758 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/050758
Bus interface unit May 14, 1987 Issued
Array ( [id] => 2401145 [patent_doc_number] => 04782487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-01 [patent_title] => 'Memory test method and apparatus' [patent_app_type] => 1 [patent_app_number] => 7/050847 [patent_app_country] => US [patent_app_date] => 1987-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4477 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/782/04782487.pdf [firstpage_image] =>[orig_patent_app_number] => 050847 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/050847
Memory test method and apparatus May 14, 1987 Issued
Array ( [id] => 2529349 [patent_doc_number] => 04856003 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-08 [patent_title] => 'Error correction code encoder' [patent_app_type] => 1 [patent_app_number] => 7/047627 [patent_app_country] => US [patent_app_date] => 1987-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4908 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/856/04856003.pdf [firstpage_image] =>[orig_patent_app_number] => 047627 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/047627
Error correction code encoder May 6, 1987 Issued
Array ( [id] => 2498877 [patent_doc_number] => 04802170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-31 [patent_title] => 'Error disbursing format for digital information and method for organizing same' [patent_app_type] => 1 [patent_app_number] => 7/043939 [patent_app_country] => US [patent_app_date] => 1987-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4030 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/802/04802170.pdf [firstpage_image] =>[orig_patent_app_number] => 043939 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/043939
Error disbursing format for digital information and method for organizing same Apr 28, 1987 Issued
Array ( [id] => 2708891 [patent_doc_number] => 04989208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-29 [patent_title] => 'Data processor' [patent_app_type] => 1 [patent_app_number] => 7/039695 [patent_app_country] => US [patent_app_date] => 1987-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3590 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/989/04989208.pdf [firstpage_image] =>[orig_patent_app_number] => 039695 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/039695
Data processor Apr 19, 1987 Issued
Menu