
Robert W. Beausoliel Jr.
Examiner (ID: 5619)
| Most Active Art Unit | 2306 |
| Art Unit(s) | 2184, 2306, 2785, 2113, 2313, 2167, 2413 |
| Total Applications | 522 |
| Issued Applications | 450 |
| Pending Applications | 14 |
| Abandoned Applications | 60 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2495785
[patent_doc_number] => 04866717
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-09-12
[patent_title] => 'Code error detecting and correcting apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/077608
[patent_app_country] => US
[patent_app_date] => 1987-07-24
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/866/04866717.pdf
[firstpage_image] =>[orig_patent_app_number] => 077608
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/077608 | Code error detecting and correcting apparatus | Jul 23, 1987 | Issued |
| 07/074848 | IN OR RELATING TO SIGNATURE ANALYSIS | Jul 16, 1987 | Abandoned |
| 07/072639 | CONVOLUTIONAL ENCODER AND SEQUENTIAL DECODER WITH PARALLEL ARCHITECTURE AND BLOCK CODING PROPERTIES | Jul 12, 1987 | Abandoned |
Array
(
[id] => 2570774
[patent_doc_number] => 04837765
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-06-06
[patent_title] => 'Test control circuit for integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 7/071068
[patent_app_country] => US
[patent_app_date] => 1987-07-08
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[firstpage_image] =>[orig_patent_app_number] => 071068
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/071068 | Test control circuit for integrated circuit | Jul 7, 1987 | Issued |
Array
(
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[patent_doc_number] => 04744084
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[patent_kind] => NA
[patent_issue_date] => 1988-05-10
[patent_title] => 'Hardware modeling system and method for simulating portions of electrical circuits'
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Array
(
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[patent_kind] => NA
[patent_issue_date] => 1989-03-28
[patent_title] => 'Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure'
[patent_app_type] => 1
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Array
(
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[patent_doc_number] => 04905242
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[patent_issue_date] => 1990-02-27
[patent_title] => 'Pipelined error detection and correction apparatus with programmable address trap'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/059696 | Pipelined error detection and correction apparatus with programmable address trap | Jun 8, 1987 | Issued |
Array
(
[id] => 2499448
[patent_doc_number] => 04868817
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[patent_issue_date] => 1989-09-19
[patent_title] => 'Circuit for preventing a microcomputer from malfunctioning'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/058269 | Circuit for preventing a microcomputer from malfunctioning | Jun 3, 1987 | Issued |
Array
(
[id] => 2501545
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[patent_title] => 'Logic circuit having individually testable logic modules'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/057078 | Logic circuit having individually testable logic modules | Jun 1, 1987 | Issued |
Array
(
[id] => 2398398
[patent_doc_number] => 04794602
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[patent_kind] => NA
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[patent_title] => 'Method for error detection'
[patent_app_type] => 1
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[firstpage_image] =>[orig_patent_app_number] => 054426
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/054426 | Method for error detection | May 25, 1987 | Issued |
Array
(
[id] => 2573427
[patent_doc_number] => 04835774
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[patent_issue_date] => 1989-05-30
[patent_title] => 'Semiconductor memory test system'
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[firstpage_image] =>[orig_patent_app_number] => 051399
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/051399 | Semiconductor memory test system | May 18, 1987 | Issued |
Array
(
[id] => 2579587
[patent_doc_number] => 04901316
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[patent_kind] => NA
[patent_issue_date] => 1990-02-13
[patent_title] => 'Disaster prevention monitoring and control facility'
[patent_app_type] => 1
[patent_app_number] => 7/050476
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[firstpage_image] =>[orig_patent_app_number] => 050476
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/050476 | Disaster prevention monitoring and control facility | May 17, 1987 | Issued |
Array
(
[id] => 2491859
[patent_doc_number] => 04823347
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[patent_issue_date] => 1989-04-18
[patent_title] => 'Deferred parity checking of control signals across a bidirectional data transmission interface'
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Array
(
[id] => 2562860
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Array
(
[id] => 2568583
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/050839 | Byte write error code method and apparatus | May 14, 1987 | Issued |
Array
(
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Array
(
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Array
(
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Array
(
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[patent_title] => 'Error disbursing format for digital information and method for organizing same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/043939 | Error disbursing format for digital information and method for organizing same | Apr 28, 1987 | Issued |
Array
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