
Robert W. Beausoliel Jr.
Examiner (ID: 5619)
| Most Active Art Unit | 2306 |
| Art Unit(s) | 2184, 2306, 2785, 2113, 2313, 2167, 2413 |
| Total Applications | 522 |
| Issued Applications | 450 |
| Pending Applications | 14 |
| Abandoned Applications | 60 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2735818
[patent_doc_number] => 05058112
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-15
[patent_title] => 'Programmable fault insertion circuit'
[patent_app_type] => 1
[patent_app_number] => 7/387037
[patent_app_country] => US
[patent_app_date] => 1989-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3226
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 567
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/058/05058112.pdf
[firstpage_image] =>[orig_patent_app_number] => 387037
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/387037 | Programmable fault insertion circuit | Jul 30, 1989 | Issued |
Array
(
[id] => 2788282
[patent_doc_number] => 05133065
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-07-21
[patent_title] => 'Backup computer program for networks'
[patent_app_type] => 1
[patent_app_number] => 7/386517
[patent_app_country] => US
[patent_app_date] => 1989-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 3115
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/133/05133065.pdf
[firstpage_image] =>[orig_patent_app_number] => 386517
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/386517 | Backup computer program for networks | Jul 26, 1989 | Issued |
Array
(
[id] => 2759226
[patent_doc_number] => 05031181
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-09
[patent_title] => 'Error correction processing apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/386787
[patent_app_country] => US
[patent_app_date] => 1989-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3436
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/031/05031181.pdf
[firstpage_image] =>[orig_patent_app_number] => 386787
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/386787 | Error correction processing apparatus | Jul 26, 1989 | Issued |
Array
(
[id] => 2642704
[patent_doc_number] => 04937827
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-06-26
[patent_title] => 'Circuit verification accessory'
[patent_app_type] => 1
[patent_app_number] => 7/385934
[patent_app_country] => US
[patent_app_date] => 1989-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 23
[patent_no_of_words] => 16317
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/937/04937827.pdf
[firstpage_image] =>[orig_patent_app_number] => 385934
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/385934 | Circuit verification accessory | Jul 24, 1989 | Issued |
| 07/382437 | ERROR RECOVERY METHOD AND APPARATUS FOR HIGH PERFORMANCE DISK DRIVES | Jul 18, 1989 | Abandoned |
Array
(
[id] => 2716299
[patent_doc_number] => 05068855
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-11-26
[patent_title] => 'Error correcting method and apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/379878
[patent_app_country] => US
[patent_app_date] => 1989-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3635
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/068/05068855.pdf
[firstpage_image] =>[orig_patent_app_number] => 379878
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/379878 | Error correcting method and apparatus | Jul 13, 1989 | Issued |
Array
(
[id] => 2759153
[patent_doc_number] => 05031177
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-09
[patent_title] => 'Method for controlling a computer-final control element and computer coupled with a final control element'
[patent_app_type] => 1
[patent_app_number] => 7/392927
[patent_app_country] => US
[patent_app_date] => 1989-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3351
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/031/05031177.pdf
[firstpage_image] =>[orig_patent_app_number] => 392927
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/392927 | Method for controlling a computer-final control element and computer coupled with a final control element | Jul 12, 1989 | Issued |
| 07/377878 | LOGIC CIRCUIT HAVING INDIVIDUALLY TESTABLE LOGIC MODULES | Jul 9, 1989 | Abandoned |
Array
(
[id] => 2827409
[patent_doc_number] => 05081627
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-14
[patent_title] => 'Status and activity monitor for contention type local area networks'
[patent_app_type] => 1
[patent_app_number] => 7/375899
[patent_app_country] => US
[patent_app_date] => 1989-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2815
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/081/05081627.pdf
[firstpage_image] =>[orig_patent_app_number] => 375899
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/375899 | Status and activity monitor for contention type local area networks | Jul 4, 1989 | Issued |
Array
(
[id] => 2817810
[patent_doc_number] => 05157668
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-20
[patent_title] => 'Method and apparatus for locating faults in electronic units'
[patent_app_type] => 1
[patent_app_number] => 7/375839
[patent_app_country] => US
[patent_app_date] => 1989-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 20
[patent_no_of_words] => 12440
[patent_no_of_claims] => 114
[patent_no_of_ind_claims] => 26
[patent_words_short_claim] => 19
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/157/05157668.pdf
[firstpage_image] =>[orig_patent_app_number] => 375839
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/375839 | Method and apparatus for locating faults in electronic units | Jul 4, 1989 | Issued |
Array
(
[id] => 2719455
[patent_doc_number] => 05042035
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-20
[patent_title] => 'Method and apparatus for controlling fault-state displaying of a subscriber\'s card in switching system'
[patent_app_type] => 1
[patent_app_number] => 7/373404
[patent_app_country] => US
[patent_app_date] => 1989-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2925
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/042/05042035.pdf
[firstpage_image] =>[orig_patent_app_number] => 373404
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/373404 | Method and apparatus for controlling fault-state displaying of a subscriber's card in switching system | Jun 29, 1989 | Issued |
Array
(
[id] => 2859345
[patent_doc_number] => 05111465
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-05-05
[patent_title] => 'Data integrity features for a sort accelerator'
[patent_app_type] => 1
[patent_app_number] => 7/374349
[patent_app_country] => US
[patent_app_date] => 1989-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 29
[patent_no_of_words] => 19311
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/111/05111465.pdf
[firstpage_image] =>[orig_patent_app_number] => 374349
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/374349 | Data integrity features for a sort accelerator | Jun 29, 1989 | Issued |
Array
(
[id] => 2744740
[patent_doc_number] => 05051998
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-24
[patent_title] => 'Data block deinterleaving and error correction system'
[patent_app_type] => 1
[patent_app_number] => 7/372585
[patent_app_country] => US
[patent_app_date] => 1989-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 14056
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/051/05051998.pdf
[firstpage_image] =>[orig_patent_app_number] => 372585
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/372585 | Data block deinterleaving and error correction system | Jun 27, 1989 | Issued |
| 07/371847 | DATA COMMUNICATION SYSTEM | Jun 26, 1989 | Abandoned |
Array
(
[id] => 2677295
[patent_doc_number] => 05070504
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-03
[patent_title] => 'Method and apparatus for providing error correction to symbol level codes'
[patent_app_type] => 1
[patent_app_number] => 7/370935
[patent_app_country] => US
[patent_app_date] => 1989-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5241
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/070/05070504.pdf
[firstpage_image] =>[orig_patent_app_number] => 370935
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/370935 | Method and apparatus for providing error correction to symbol level codes | Jun 22, 1989 | Issued |
Array
(
[id] => 2677259
[patent_doc_number] => 05070502
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-03
[patent_title] => 'Defect tolerant set associative cache'
[patent_app_type] => 1
[patent_app_number] => 7/370469
[patent_app_country] => US
[patent_app_date] => 1989-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6061
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/070/05070502.pdf
[firstpage_image] =>[orig_patent_app_number] => 370469
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/370469 | Defect tolerant set associative cache | Jun 22, 1989 | Issued |
Array
(
[id] => 2720303
[patent_doc_number] => 05018146
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-21
[patent_title] => 'Apparatus and method for determining if a particular plug-in card is appropriate for use with an electronic processor'
[patent_app_type] => 1
[patent_app_number] => 7/369898
[patent_app_country] => US
[patent_app_date] => 1989-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 4
[patent_no_of_words] => 3234
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/018/05018146.pdf
[firstpage_image] =>[orig_patent_app_number] => 369898
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/369898 | Apparatus and method for determining if a particular plug-in card is appropriate for use with an electronic processor | Jun 21, 1989 | Issued |
Array
(
[id] => 2716376
[patent_doc_number] => 05068859
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-11-26
[patent_title] => 'Large constraint length high speed viterbi decoder based on a modular hierarchial decomposition of the deBruijn graph'
[patent_app_type] => 1
[patent_app_number] => 7/368264
[patent_app_country] => US
[patent_app_date] => 1989-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 6340
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/068/05068859.pdf
[firstpage_image] =>[orig_patent_app_number] => 368264
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/368264 | Large constraint length high speed viterbi decoder based on a modular hierarchial decomposition of the deBruijn graph | Jun 18, 1989 | Issued |
Array
(
[id] => 2755458
[patent_doc_number] => 05023873
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-06-11
[patent_title] => 'Method and apparatus for communication link management'
[patent_app_type] => 1
[patent_app_number] => 7/366947
[patent_app_country] => US
[patent_app_date] => 1989-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 7580
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/023/05023873.pdf
[firstpage_image] =>[orig_patent_app_number] => 366947
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/366947 | Method and apparatus for communication link management | Jun 14, 1989 | Issued |
Array
(
[id] => 2706691
[patent_doc_number] => 04991176
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-02-05
[patent_title] => 'Optimal test generation for finite state machine models'
[patent_app_type] => 1
[patent_app_number] => 7/362724
[patent_app_country] => US
[patent_app_date] => 1989-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5882
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/991/04991176.pdf
[firstpage_image] =>[orig_patent_app_number] => 362724
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/362724 | Optimal test generation for finite state machine models | Jun 6, 1989 | Issued |