Robert W. Hodge

Array ( [id] => 17933615 [patent_doc_number] => 20220328741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => LIGHT EMITTING MODULE AND METHOD OF MANUFACTURING LIGHT EMITTING MODULE [patent_app_type] => utility [patent_app_number] => 17/702245 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17702245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17723386 [patent_doc_number] => 20220216108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => METHODS FOR DICING SEMICONDUCTOR WAFERS AND SEMICONDUCTOR DEVICES MADE BY THE METHODS [patent_app_type] => utility [patent_app_number] => 17/702126 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17702126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19765971 [patent_doc_number] => 12224272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Manufacturing micro-LED displays to reduce subpixel crosstalk [patent_app_type] => utility [patent_app_number] => 17/701599 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 44 [patent_no_of_words] => 6285 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17871122 [patent_doc_number] => 20220293859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => FLEXIBLE AND STRETCHABLE SEMICONDUCTOR DEVICES WITH REDUCED FOOTPRINTS AND METHODS THEREFOR [patent_app_type] => utility [patent_app_number] => 17/694577 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18999211 [patent_doc_number] => 11916067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => High reliability polysilicon components [patent_app_type] => utility [patent_app_number] => 17/684774 [patent_app_country] => US [patent_app_date] => 2022-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 5240 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17684774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19087928 [patent_doc_number] => 20240114729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => DISPLAY PANEL AND UNDER-SCREEN CAMERA DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/762098 [patent_app_country] => US [patent_app_date] => 2022-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17762098 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18999130 [patent_doc_number] => 11915986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Ceramic semiconductor device package with copper tungsten conductive layers [patent_app_type] => utility [patent_app_number] => 17/683308 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5735 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18081344 [patent_doc_number] => 20220406956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => INTEGRATED CIRCUIT WITH A GALVANICALLY-ISOLATED COMMUINCATION CHANNEL USING A BACK-SIDE ETCHED CHANNEL [patent_app_type] => utility [patent_app_number] => 17/680981 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18081344 [patent_doc_number] => 20220406956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => INTEGRATED CIRCUIT WITH A GALVANICALLY-ISOLATED COMMUINCATION CHANNEL USING A BACK-SIDE ETCHED CHANNEL [patent_app_type] => utility [patent_app_number] => 17/680981 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19130828 [patent_doc_number] => 20240136181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, APPARATUS FOR MANUFACTURING THE SAME, AND TEMPLATE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/278795 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18278795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19130828 [patent_doc_number] => 20240136181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, APPARATUS FOR MANUFACTURING THE SAME, AND TEMPLATE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/278795 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18278795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19567738 [patent_doc_number] => 12142516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Self aligned buried power rail [patent_app_type] => utility [patent_app_number] => 17/678437 [patent_app_country] => US [patent_app_date] => 2022-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17678437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19945453 [patent_doc_number] => 12317603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Process for protecting an upper stage of electronic components of an integrated circuit against antenna effects [patent_app_type] => utility [patent_app_number] => 17/652166 [patent_app_country] => US [patent_app_date] => 2022-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 941 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17652166 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20435957 [patent_doc_number] => 12507428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Semiconductor device including transistor portion and diode portion [patent_app_type] => utility [patent_app_number] => 17/679057 [patent_app_country] => US [patent_app_date] => 2022-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5877 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17679057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18759876 [patent_doc_number] => 11810916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Semiconductor capacitor array layout capable of generating parasitic capacitance toward edge of layout [patent_app_type] => utility [patent_app_number] => 17/676855 [patent_app_country] => US [patent_app_date] => 2022-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4439 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18170082 [patent_doc_number] => 20230036693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => Semiconductor Devices and Methods of Manufacture [patent_app_type] => utility [patent_app_number] => 17/675558 [patent_app_country] => US [patent_app_date] => 2022-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17675558 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18585960 [patent_doc_number] => 20230268225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/651615 [patent_app_country] => US [patent_app_date] => 2022-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17651615 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18195081 [patent_doc_number] => 20230048600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/651574 [patent_app_country] => US [patent_app_date] => 2022-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5331 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17651574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18767081 [patent_doc_number] => 11817495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/672721 [patent_app_country] => US [patent_app_date] => 2022-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12644 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18857239 [patent_doc_number] => 11854832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Semiconductor device structure having a profile modifier [patent_app_type] => utility [patent_app_number] => 17/665722 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 7857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665722 [rel_patent_id] =>[rel_patent_doc_number] =>)