Search

Robert W. Hodge

Supervisory Patent Examiner (ID: 10805, Phone: (571)272-2097 , Office: P/3655 )

Most Active Art Unit
1795
Art Unit(s)
3655, 1795, 4121, 1746, 1745, 1729, 3649, 3645
Total Applications
436
Issued Applications
181
Pending Applications
28
Abandoned Applications
231

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17615505 [patent_doc_number] => 20220157785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => 3D INTEGRATED CIRCUIT (3DIC) STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/649381 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17649381 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/649381
3D INTEGRATED CIRCUIT (3DIC) STRUCTURE Jan 30, 2022 Pending
Array ( [id] => 19974092 [patent_doc_number] => 12342727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Magnetoresistive random-access memory (MRAM) structure for improving process control and method of fabricating thereof [patent_app_type] => utility [patent_app_number] => 17/589018 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589018 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/589018
Magnetoresistive random-access memory (MRAM) structure for improving process control and method of fabricating thereof Jan 30, 2022 Issued
Array ( [id] => 17599429 [patent_doc_number] => 20220149003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => FLIP-CHIP ON LEADFRAME HAVING PARTIALLY ETCHED LANDING SITES [patent_app_type] => utility [patent_app_number] => 17/584070 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584070 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/584070
FLIP-CHIP ON LEADFRAME HAVING PARTIALLY ETCHED LANDING SITES Jan 24, 2022 Pending
Array ( [id] => 17599429 [patent_doc_number] => 20220149003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => FLIP-CHIP ON LEADFRAME HAVING PARTIALLY ETCHED LANDING SITES [patent_app_type] => utility [patent_app_number] => 17/584070 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584070 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/584070
FLIP-CHIP ON LEADFRAME HAVING PARTIALLY ETCHED LANDING SITES Jan 24, 2022 Pending
Array ( [id] => 19828875 [patent_doc_number] => 12249671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Nanorod light emitting device, substrate structure including a plurality of nanorod light emitting devices, and method of manufacturing the substrate structure [patent_app_type] => utility [patent_app_number] => 17/582172 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 12857 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582172 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/582172
Nanorod light emitting device, substrate structure including a plurality of nanorod light emitting devices, and method of manufacturing the substrate structure Jan 23, 2022 Issued
Array ( [id] => 19812520 [patent_doc_number] => 12243933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Semiconductor device layouts [patent_app_type] => utility [patent_app_number] => 17/570198 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 57 [patent_no_of_words] => 7517 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 514 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570198 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/570198
Semiconductor device layouts Jan 5, 2022 Issued
Array ( [id] => 19315958 [patent_doc_number] => 12041794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Semiconductor storage device comprising staircase portion [patent_app_type] => utility [patent_app_number] => 17/569567 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 5607 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569567 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569567
Semiconductor storage device comprising staircase portion Jan 5, 2022 Issued
Array ( [id] => 17582978 [patent_doc_number] => 20220139833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => INTERCONNECTION STRUCTURE LINED BY ISOLATION LAYER [patent_app_type] => utility [patent_app_number] => 17/569831 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569831 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569831
INTERCONNECTION STRUCTURE LINED BY ISOLATION LAYER Jan 5, 2022 Pending
Array ( [id] => 18210812 [patent_doc_number] => 20230057074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => RF SWITCH DEVICE AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/569382 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569382 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569382
RF switch device having a highly resistive substrate, an isolation layer therein or thereon, and a trap-rich layer therein or thereon Jan 4, 2022 Issued
Array ( [id] => 17551535 [patent_doc_number] => 20220122877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH AT LEAST TWO SINGLE-CRYSTAL LAYERS [patent_app_type] => utility [patent_app_number] => 17/566690 [patent_app_country] => US [patent_app_date] => 2021-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 79487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566690 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566690
3D semiconductor devices and structures with at least two single-crystal layers Dec 30, 2021 Issued
Array ( [id] => 17933400 [patent_doc_number] => 20220328526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/566082 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566082 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566082
Semiconductor device with metal structure Dec 29, 2021 Issued
Array ( [id] => 19168532 [patent_doc_number] => 11984446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Semiconductor device with capacitors having different dielectric layer heights [patent_app_type] => utility [patent_app_number] => 17/565248 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 39 [patent_no_of_words] => 7412 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/565248
Semiconductor device with capacitors having different dielectric layer heights Dec 28, 2021 Issued
Array ( [id] => 17536825 [patent_doc_number] => 20220115434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => METHOD OF FORMING SHALLOW TRENCH ISOLATION (STI) STRUCTURE FOR SUPPRESSING DARK CURRENT [patent_app_type] => utility [patent_app_number] => 17/558858 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558858 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/558858
Method of forming shallow trench isolation (STI) structure for suppressing dark current Dec 21, 2021 Issued
Array ( [id] => 20191376 [patent_doc_number] => 12402518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Display panel with reduced gas breaking and foreign matter invasion and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/622843 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17622843 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/622843
Display panel with reduced gas breaking and foreign matter invasion and manufacturing method thereof Dec 20, 2021 Issued
Array ( [id] => 19016345 [patent_doc_number] => 11923287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Method for manufacturing semiconductor device having chip stacked and molded [patent_app_type] => utility [patent_app_number] => 17/545709 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 5167 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545709 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/545709
Method for manufacturing semiconductor device having chip stacked and molded Dec 7, 2021 Issued
Array ( [id] => 17485936 [patent_doc_number] => 20220093440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH REDUNDANCY [patent_app_type] => utility [patent_app_number] => 17/542492 [patent_app_country] => US [patent_app_date] => 2021-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 79460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542492
3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits Dec 4, 2021 Issued
Array ( [id] => 18882853 [patent_doc_number] => 20240006222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/255383 [patent_app_country] => US [patent_app_date] => 2021-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18255383 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/255383
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Dec 1, 2021 Pending
Array ( [id] => 18882853 [patent_doc_number] => 20240006222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/255383 [patent_app_country] => US [patent_app_date] => 2021-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18255383 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/255383
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Dec 1, 2021 Pending
Array ( [id] => 18047930 [patent_doc_number] => 11521888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => 3D semiconductor device and structure with high-k metal gate transistors [patent_app_type] => utility [patent_app_number] => 17/536097 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 346 [patent_no_of_words] => 79837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536097 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/536097
3D semiconductor device and structure with high-k metal gate transistors Nov 28, 2021 Issued
Array ( [id] => 17764816 [patent_doc_number] => 20220238429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF [patent_app_type] => utility [patent_app_number] => 17/533017 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17533017 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/533017
Semiconductor devices including decoupling capacitors and methods of manufacturing thereof Nov 21, 2021 Issued
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