Search

Robert W. Hodge

Supervisory Patent Examiner (ID: 10805, Phone: (571)272-2097 , Office: P/3655 )

Most Active Art Unit
1795
Art Unit(s)
3655, 1795, 4121, 1746, 1745, 1729, 3649, 3645
Total Applications
436
Issued Applications
181
Pending Applications
28
Abandoned Applications
231

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18866030 [patent_doc_number] => 20230420467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => SOLID-STATE IMAGING ELEMENT [patent_app_type] => utility [patent_app_number] => 18/254021 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18254021 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/254021
SOLID-STATE IMAGING ELEMENT Nov 16, 2021 Pending
Array ( [id] => 18359204 [patent_doc_number] => 11647623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Method for manufacturing semiconductor structure with buried power line and buried signal line [patent_app_type] => utility [patent_app_number] => 17/524917 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 7443 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/524917
Method for manufacturing semiconductor structure with buried power line and buried signal line Nov 11, 2021 Issued
Array ( [id] => 19796356 [patent_doc_number] => 12237327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Variable width for RF neighboring stacks [patent_app_type] => utility [patent_app_number] => 17/523816 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4421 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523816 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523816
Variable width for RF neighboring stacks Nov 9, 2021 Issued
Array ( [id] => 18346269 [patent_doc_number] => 20230134379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => LATTICE STACK FOR INTERNAL SPACER FABRICATION [patent_app_type] => utility [patent_app_number] => 17/517925 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517925 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517925
LATTICE STACK FOR INTERNAL SPACER FABRICATION Nov 2, 2021 Pending
Array ( [id] => 19371692 [patent_doc_number] => 12063797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Buried connection line for peripheral area of a memory device [patent_app_type] => utility [patent_app_number] => 17/513489 [patent_app_country] => US [patent_app_date] => 2021-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7108 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17513489 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/513489
Buried connection line for peripheral area of a memory device Oct 27, 2021 Issued
Array ( [id] => 19153898 [patent_doc_number] => 11978822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Method of manufacturing light-emitting device including phosphor pieces [patent_app_type] => utility [patent_app_number] => 17/511049 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 6320 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17511049 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/511049
Method of manufacturing light-emitting device including phosphor pieces Oct 25, 2021 Issued
Array ( [id] => 18591660 [patent_doc_number] => 11740553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Method of manufacturing photomask set for forming patterns [patent_app_type] => utility [patent_app_number] => 17/510665 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 62 [patent_no_of_words] => 12898 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510665 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510665
Method of manufacturing photomask set for forming patterns Oct 25, 2021 Issued
Array ( [id] => 18767369 [patent_doc_number] => 11817786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Embedded substrate voltage converter module [patent_app_type] => utility [patent_app_number] => 17/508078 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7445 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508078 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/508078
Embedded substrate voltage converter module Oct 21, 2021 Issued
Array ( [id] => 19046809 [patent_doc_number] => 11935929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => High aspect ratio shared contacts [patent_app_type] => utility [patent_app_number] => 17/507385 [patent_app_country] => US [patent_app_date] => 2021-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6833 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17507385 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/507385
High aspect ratio shared contacts Oct 20, 2021 Issued
Array ( [id] => 18608258 [patent_doc_number] => 11749737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Memory device with bottom-select-gate structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/500340 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 11206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500340 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/500340
Memory device with bottom-select-gate structure and method for forming the same Oct 12, 2021 Issued
Array ( [id] => 18564724 [patent_doc_number] => 11729994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Structures for testing nanoscale devices including ferroelectric capacitors and methods for forming the same [patent_app_type] => utility [patent_app_number] => 17/496857 [patent_app_country] => US [patent_app_date] => 2021-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 9481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496857 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/496857
Structures for testing nanoscale devices including ferroelectric capacitors and methods for forming the same Oct 7, 2021 Issued
Array ( [id] => 19943647 [patent_doc_number] => 12315783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Integrated circuit with a ring-shaped hot spot area and multidirectional cooling [patent_app_type] => utility [patent_app_number] => 17/484766 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8247 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17484766 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/484766
Integrated circuit with a ring-shaped hot spot area and multidirectional cooling Sep 23, 2021 Issued
Array ( [id] => 18789236 [patent_doc_number] => 20230377880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => ELECTRONICS UNIT AND METHOD FOR THE PRODUCTION THEREOF [patent_app_type] => utility [patent_app_number] => 18/246394 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18246394 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/246394
ELECTRONICS UNIT AND METHOD FOR THE PRODUCTION THEREOF Sep 23, 2021 Pending
Array ( [id] => 18789236 [patent_doc_number] => 20230377880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => ELECTRONICS UNIT AND METHOD FOR THE PRODUCTION THEREOF [patent_app_type] => utility [patent_app_number] => 18/246394 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18246394 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/246394
ELECTRONICS UNIT AND METHOD FOR THE PRODUCTION THEREOF Sep 23, 2021 Pending
Array ( [id] => 18280136 [patent_doc_number] => 20230095608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => CONFORMAL POWER DELIVERY STRUCTURES INCLUDING EMBEDDED PASSIVE DEVICES [patent_app_type] => utility [patent_app_number] => 17/485250 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485250 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485250
CONFORMAL POWER DELIVERY STRUCTURES INCLUDING EMBEDDED PASSIVE DEVICES Sep 23, 2021 Pending
Array ( [id] => 18945743 [patent_doc_number] => 20240040882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 17/610977 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17610977 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/610977
DISPLAY PANEL Sep 16, 2021 Pending
Array ( [id] => 18945743 [patent_doc_number] => 20240040882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 17/610977 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17610977 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/610977
DISPLAY PANEL Sep 16, 2021 Pending
Array ( [id] => 18254843 [patent_doc_number] => 20230081882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => STACKED MEMORY STRUCTURE WITH DUAL-CHANNEL TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/474689 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17474689 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/474689
STACKED MEMORY STRUCTURE WITH DUAL-CHANNEL TRANSISTOR Sep 13, 2021 Pending
Array ( [id] => 18254843 [patent_doc_number] => 20230081882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => STACKED MEMORY STRUCTURE WITH DUAL-CHANNEL TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/474689 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17474689 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/474689
STACKED MEMORY STRUCTURE WITH DUAL-CHANNEL TRANSISTOR Sep 13, 2021 Pending
Array ( [id] => 17318792 [patent_doc_number] => 20210407842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => METHOD FOR PRODUCING A 3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/473224 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 79675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473224 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/473224
Methods for producing 3D semiconductor memory device and structure utilizing alignment marks Sep 12, 2021 Issued
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