Robert W. Hodge

Array ( [id] => 18251060 [patent_doc_number] => 20230078099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => PATCH PACKAGING ARCHITECTURE IMPLEMENTING HYBRID BONDS AND SELF-ALIGNED TEMPLATE [patent_app_type] => utility [patent_app_number] => 17/473414 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473414 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18251060 [patent_doc_number] => 20230078099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => PATCH PACKAGING ARCHITECTURE IMPLEMENTING HYBRID BONDS AND SELF-ALIGNED TEMPLATE [patent_app_type] => utility [patent_app_number] => 17/473414 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473414 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17303142 [patent_doc_number] => 20210398981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => Asymmetric Semiconductor Memory Device Having Electrically Floating Body Transistor [patent_app_type] => utility [patent_app_number] => 17/467400 [patent_app_country] => US [patent_app_date] => 2021-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33114 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18243194 [patent_doc_number] => 20230075505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => METAL PILLAR CONNECTION TOPOLOGIES FOR HETEROGENEOUS PACKAGING [patent_app_type] => utility [patent_app_number] => 17/466783 [patent_app_country] => US [patent_app_date] => 2021-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15992 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17466783 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18228356 [patent_doc_number] => 20230067350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => DUMMY METAL BONDING PADS FOR UNDERFILL APPLICATION IN SEMICONDUCTOR DIE PACKAGING AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/462066 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18587684 [patent_doc_number] => 20230269949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => METAL OXIDE FILM, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/043669 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 63976 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18043669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17840805 [patent_doc_number] => 20220278111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FORMING A SRAM MEMORY CELL STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/410860 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17278184 [patent_doc_number] => 20210384382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => Light emitting device with reflector [patent_app_type] => utility [patent_app_number] => 17/407325 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17278111 [patent_doc_number] => 20210384309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => METHOD FOR FORMING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/445434 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18617772 [patent_doc_number] => 20230284513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => DISPLAY DEVICE, METHOD OF MANUFACTURING DISPLAY DEVICE, AND ELECTRONIC APPARATUS USING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/016738 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18016738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19138141 [patent_doc_number] => 11973117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/392320 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 11538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17392320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17339602 [patent_doc_number] => 20220005933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => VARIED SILICON RICHNESS SILICON NITRIDE FORMATION [patent_app_type] => utility [patent_app_number] => 17/376468 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17196005 [patent_doc_number] => 11164770 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-02 [patent_title] => Method for producing a 3D semiconductor memory device and structure [patent_app_type] => utility [patent_app_number] => 17/372776 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 343 [patent_no_of_words] => 79515 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18624003 [patent_doc_number] => 11757061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Microelectronic workpiece processing systems and associated methods of color correction [patent_app_type] => utility [patent_app_number] => 17/373200 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4838 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17373200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20082720 [patent_doc_number] => 12356822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Oled display panel having multiple light-emitting layers and a pixel definition layer provided with openings, and preparation method therefor, and display apparatus [patent_app_type] => utility [patent_app_number] => 17/771824 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17771824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18040345 [patent_doc_number] => 20220384562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => CAPACITOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/359655 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20471125 [patent_doc_number] => 12527173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Display substrate having planarization layer covering spacing region between signal lines, manufacturing method thereof and display apparatus [patent_app_type] => utility [patent_app_number] => 17/782979 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 4256 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17782979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20471125 [patent_doc_number] => 12527173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Display substrate having planarization layer covering spacing region between signal lines, manufacturing method thereof and display apparatus [patent_app_type] => utility [patent_app_number] => 17/782979 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 4256 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17782979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19168409 [patent_doc_number] => 11984321 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-05-14 [patent_title] => Method for etching deep, high-aspect ratio features into silicon carbide and gallium nitride [patent_app_type] => utility [patent_app_number] => 17/358140 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 40 [patent_no_of_words] => 12726 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18097681 [patent_doc_number] => 20220416022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => SUBSTRATE-LESS NANOWIRE-BASED LATERAL DIODE INTEGRATED CIRCUIT STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/357767 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17357767 [rel_patent_id] =>[rel_patent_doc_number] =>)