
Robert W. Hodge
Supervisory Patent Examiner (ID: 10805, Phone: (571)272-2097 , Office: P/3655 )
| Most Active Art Unit | 1795 |
| Art Unit(s) | 3655, 1795, 4121, 1746, 1745, 1729, 3649, 3645 |
| Total Applications | 436 |
| Issued Applications | 181 |
| Pending Applications | 28 |
| Abandoned Applications | 231 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17130400
[patent_doc_number] => 20210305169
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-30
[patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 17/191819
[patent_app_country] => US
[patent_app_date] => 2021-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6211
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 20
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17191819
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/191819 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR SUBSTRATE | Mar 3, 2021 | Abandoned |
Array
(
[id] => 19488855
[patent_doc_number] => 12108598
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-01
[patent_title] => Semiconductor storage device with pillar
[patent_app_type] => utility
[patent_app_number] => 17/190739
[patent_app_country] => US
[patent_app_date] => 2021-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 34
[patent_no_of_words] => 8309
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190739
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/190739 | Semiconductor storage device with pillar | Mar 2, 2021 | Issued |
Array
(
[id] => 17359957
[patent_doc_number] => 20220020753
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-20
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/185102
[patent_app_country] => US
[patent_app_date] => 2021-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13228
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185102
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/185102 | Semiconductor device having a node capping pattern and a gate capping pattern | Feb 24, 2021 | Issued |
Array
(
[id] => 18190710
[patent_doc_number] => 11581312
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-14
[patent_title] => Semiconductor devices having different numbers of stacked channels in different regions and methods of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/173546
[patent_app_country] => US
[patent_app_date] => 2021-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 14163
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173546
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/173546 | Semiconductor devices having different numbers of stacked channels in different regions and methods of manufacturing the same | Feb 10, 2021 | Issued |
Array
(
[id] => 19399761
[patent_doc_number] => 12074149
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-27
[patent_title] => Device packages with uniform components and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 17/168251
[patent_app_country] => US
[patent_app_date] => 2021-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 31
[patent_no_of_words] => 19774
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168251
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/168251 | Device packages with uniform components and methods of forming the same | Feb 4, 2021 | Issued |
Array
(
[id] => 18623744
[patent_doc_number] => 11756799
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-09-12
[patent_title] => 3D printed ceramic structure with metal traces
[patent_app_type] => utility
[patent_app_number] => 17/165825
[patent_app_country] => US
[patent_app_date] => 2021-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5776
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165825
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/165825 | 3D printed ceramic structure with metal traces | Feb 1, 2021 | Issued |
Array
(
[id] => 19814031
[patent_doc_number] => 12245463
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-04
[patent_title] => Display panel and display device having detection circuit and light-emitting device
[patent_app_type] => utility
[patent_app_number] => 17/637772
[patent_app_country] => US
[patent_app_date] => 2021-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 7605
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17637772
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/637772 | Display panel and display device having detection circuit and light-emitting device | Feb 1, 2021 | Issued |
Array
(
[id] => 18165456
[patent_doc_number] => 20230032055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-02
[patent_title] => ELECTRON-GAS THERMOELECTRIC SENSOR
[patent_app_type] => utility
[patent_app_number] => 17/758720
[patent_app_country] => US
[patent_app_date] => 2021-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8718
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17758720
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/758720 | ELECTRON-GAS THERMOELECTRIC SENSOR | Jan 13, 2021 | Abandoned |
Array
(
[id] => 19244660
[patent_doc_number] => 12015115
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-18
[patent_title] => Optoelectronic modules having fluid permeable channels and methods for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/148087
[patent_app_country] => US
[patent_app_date] => 2021-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 27
[patent_no_of_words] => 6757
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148087
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/148087 | Optoelectronic modules having fluid permeable channels and methods for manufacturing the same | Jan 12, 2021 | Issued |
Array
(
[id] => 16845946
[patent_doc_number] => 11018042
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-05-25
[patent_title] => 3D semiconductor memory device and structure
[patent_app_type] => utility
[patent_app_number] => 17/145296
[patent_app_country] => US
[patent_app_date] => 2021-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 83
[patent_figures_cnt] => 343
[patent_no_of_words] => 79712
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145296
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/145296 | 3D semiconductor memory device and structure | Jan 8, 2021 | Issued |
Array
(
[id] => 16858363
[patent_doc_number] => 20210159108
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-27
[patent_title] => METHOD FOR PROCESSING A 3D INTEGRATED CIRCUIT AND STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/140130
[patent_app_country] => US
[patent_app_date] => 2021-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 79505
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140130
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/140130 | Method for processing a 3D integrated circuit and structure | Jan 2, 2021 | Issued |
Array
(
[id] => 18396931
[patent_doc_number] => 20230165152
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-25
[patent_title] => LITHIUM NIOBATE SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/771351
[patent_app_country] => US
[patent_app_date] => 2020-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8307
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17771351
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/771351 | Lithium niobate semiconductor structure and manufacturing method thereof | Dec 27, 2020 | Issued |
Array
(
[id] => 18396931
[patent_doc_number] => 20230165152
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-25
[patent_title] => LITHIUM NIOBATE SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/771351
[patent_app_country] => US
[patent_app_date] => 2020-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8307
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17771351
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/771351 | Lithium niobate semiconductor structure and manufacturing method thereof | Dec 27, 2020 | Issued |
Array
(
[id] => 16865920
[patent_doc_number] => 11024673
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-06-01
[patent_title] => 3D semiconductor device and structure
[patent_app_type] => utility
[patent_app_number] => 17/121741
[patent_app_country] => US
[patent_app_date] => 2020-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 80
[patent_figures_cnt] => 84
[patent_no_of_words] => 10592
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121741
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/121741 | 3D semiconductor device and structure | Dec 13, 2020 | Issued |
Array
(
[id] => 16920577
[patent_doc_number] => 20210193669
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-24
[patent_title] => SRAM LAYOUT WITH SMALL FOOTPRINT AND EFFICIENT ASPECT RATIO
[patent_app_type] => utility
[patent_app_number] => 17/118372
[patent_app_country] => US
[patent_app_date] => 2020-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12458
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118372
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/118372 | SRAM cell layout including arrangement of multiple active regions and multiple gate regions | Dec 9, 2020 | Issued |
Array
(
[id] => 18111971
[patent_doc_number] => 20230004851
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-05
[patent_title] => SYSTEMS AND METHODS FOR FABRICATING SUPERCONDUCTING INTEGRATED CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 17/782261
[patent_app_country] => US
[patent_app_date] => 2020-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14091
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -45
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17782261
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/782261 | Systems and methods for fabricating flux trap mitigating superconducting integrated circuits | Dec 2, 2020 | Issued |
Array
(
[id] => 18111971
[patent_doc_number] => 20230004851
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-05
[patent_title] => SYSTEMS AND METHODS FOR FABRICATING SUPERCONDUCTING INTEGRATED CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 17/782261
[patent_app_country] => US
[patent_app_date] => 2020-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14091
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -45
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17782261
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/782261 | Systems and methods for fabricating flux trap mitigating superconducting integrated circuits | Dec 2, 2020 | Issued |
Array
(
[id] => 18528758
[patent_doc_number] => 11715763
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-01
[patent_title] => Method of forming metal contact for semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/107471
[patent_app_country] => US
[patent_app_date] => 2020-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 36
[patent_no_of_words] => 10704
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107471
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/107471 | Method of forming metal contact for semiconductor device | Nov 29, 2020 | Issued |
Array
(
[id] => 16692205
[patent_doc_number] => 20210074684
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-11
[patent_title] => STRUCTURE AND FORMATION METHOD FOR CHIP PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/099395
[patent_app_country] => US
[patent_app_date] => 2020-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9832
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17099395
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/099395 | Stacked chip package and methods of manufacture thereof | Nov 15, 2020 | Issued |
Array
(
[id] => 17615391
[patent_doc_number] => 20220157671
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-19
[patent_title] => PACKAGED RF POWER DEVICE WITH PCB ROUTING
[patent_app_type] => utility
[patent_app_number] => 17/097294
[patent_app_country] => US
[patent_app_date] => 2020-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11691
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097294
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/097294 | Packaged RF power device with PCB routing outside protective member | Nov 12, 2020 | Issued |