Search

Robert W. Hodge

Supervisory Patent Examiner (ID: 10805, Phone: (571)272-2097 , Office: P/3655 )

Most Active Art Unit
1795
Art Unit(s)
3655, 1795, 4121, 1746, 1745, 1729, 3649, 3645
Total Applications
436
Issued Applications
181
Pending Applications
28
Abandoned Applications
231

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16479760 [patent_doc_number] => 10854716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Semiconductor device with source/drain contact formed using bottom-up deposition [patent_app_type] => utility [patent_app_number] => 16/252405 [patent_app_country] => US [patent_app_date] => 2019-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 36 [patent_no_of_words] => 10622 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16252405 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/252405
Semiconductor device with source/drain contact formed using bottom-up deposition Jan 17, 2019 Issued
Array ( [id] => 16796323 [patent_doc_number] => 20210126140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => SURFACE MOUNT SOLAR CELL HAVING LOW STRESS PASSIVATION LAYERS [patent_app_type] => utility [patent_app_number] => 16/963193 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16963193 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/963193
SURFACE MOUNT SOLAR CELL HAVING LOW STRESS PASSIVATION LAYERS Jan 16, 2019 Abandoned
Array ( [id] => 16180500 [patent_doc_number] => 20200227469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => III-N TRANSISTORS INTEGRATED WITH RESONATORS OF RADIO FREQUENCY FILTERS [patent_app_type] => utility [patent_app_number] => 16/249493 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249493 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249493
III-N TRANSISTORS INTEGRATED WITH RESONATORS OF RADIO FREQUENCY FILTERS Jan 15, 2019 Abandoned
Array ( [id] => 18001061 [patent_doc_number] => 11502172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Semiconductor device with carbon-density-decreasing region [patent_app_type] => utility [patent_app_number] => 16/962160 [patent_app_country] => US [patent_app_date] => 2019-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 13369 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16962160 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/962160
Semiconductor device with carbon-density-decreasing region Jan 9, 2019 Issued
Array ( [id] => 16528987 [patent_doc_number] => 20200403068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => A METHOD OF MAKING A GRAPHENE TRANSISTOR AND DEVICES [patent_app_type] => utility [patent_app_number] => 16/961089 [patent_app_country] => US [patent_app_date] => 2019-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16961089 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/961089
A METHOD OF MAKING A GRAPHENE TRANSISTOR AND DEVICES Jan 9, 2019 Abandoned
Array ( [id] => 14573385 [patent_doc_number] => 20190214300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => DEVICES FOR FABRICATION OF SHIELDED MODULES [patent_app_type] => utility [patent_app_number] => 16/231456 [patent_app_country] => US [patent_app_date] => 2018-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231456 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/231456
Devices for fabrication of shielded modules Dec 21, 2018 Issued
Array ( [id] => 16098545 [patent_doc_number] => 20200203259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => INTEGRATED CIRCUIT PACKAGE [patent_app_type] => utility [patent_app_number] => 16/230837 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16230837 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/230837
INTEGRATED CIRCUIT PACKAGE Dec 20, 2018 Abandoned
Array ( [id] => 16098967 [patent_doc_number] => 20200203470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => MAGNETIC MOLD MATERIAL INDUCTORS FOR ELECTRONIC PACKAGES [patent_app_type] => utility [patent_app_number] => 16/226745 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226745 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226745
MAGNETIC MOLD MATERIAL INDUCTORS FOR ELECTRONIC PACKAGES Dec 19, 2018 Abandoned
Array ( [id] => 16448286 [patent_doc_number] => 10840217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Stacked chip package and methods of manufacture thereof [patent_app_type] => utility [patent_app_number] => 16/225665 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 39 [patent_no_of_words] => 9827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16225665 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/225665
Stacked chip package and methods of manufacture thereof Dec 18, 2018 Issued
Array ( [id] => 17769237 [patent_doc_number] => 11401162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Method for transferring a useful layer into a supporting substrate [patent_app_type] => utility [patent_app_number] => 16/223857 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 27 [patent_no_of_words] => 5467 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16223857 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/223857
Method for transferring a useful layer into a supporting substrate Dec 17, 2018 Issued
Array ( [id] => 17389757 [patent_doc_number] => 20220037609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => DISPLAY DEVICE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/298847 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17298847 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/298847
Display device including electron transport layer having nanoparticle of metal oxide Dec 10, 2018 Issued
Array ( [id] => 18156402 [patent_doc_number] => 11569397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Hybrid transparent conducting electrode [patent_app_type] => utility [patent_app_number] => 16/769991 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4978 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16769991 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/769991
Hybrid transparent conducting electrode Dec 5, 2018 Issued
Array ( [id] => 17438911 [patent_doc_number] => 11264251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Method of manufacturing power amplifier package embedded with input-output circuit [patent_app_type] => utility [patent_app_number] => 16/766483 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1860 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16766483 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/766483
Method of manufacturing power amplifier package embedded with input-output circuit Nov 28, 2018 Issued
Array ( [id] => 15969569 [patent_doc_number] => 20200168536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => ASYMMETRIC CORED INTEGRATED CIRCUIT PACKAGE SUPPORTS [patent_app_type] => utility [patent_app_number] => 16/202690 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202690 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202690
Asymmetric cored integrated circuit package supports Nov 27, 2018 Issued
Array ( [id] => 17232495 [patent_doc_number] => 20210359052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => DISPLAY PANEL AND DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 16/319353 [patent_app_country] => US [patent_app_date] => 2018-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6161 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16319353 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/319353
Display panel where opening rates of first and second subpixels are less than that of a third subpixel while channel ratios of the first and second subpixels are greater than that of the third subpixel and display apparatus Nov 20, 2018 Issued
Array ( [id] => 14316795 [patent_doc_number] => 20190148101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => MICROELECTROMECHANICAL LIGHT EMITTER COMPONENT, LIGHT EMITTER COMPONENT AND METHOD FOR PRODUCING A MICROELECTROMECHANICAL LIGHT EMITTER COMPONENT [patent_app_type] => utility [patent_app_number] => 16/186678 [patent_app_country] => US [patent_app_date] => 2018-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8597 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16186678 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/186678
Microelectromechanical light emitter component, light emitter component and method for producing a microelectromechanical light emitter component Nov 11, 2018 Issued
Array ( [id] => 16345461 [patent_doc_number] => 20200310112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => METHOD FOR REMOVING FOREIGN MATTER AND METHOD FOR MANUFACTURING OPTICAL DETECTION DEVICE [patent_app_type] => utility [patent_app_number] => 16/765577 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16765577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/765577
Method for removing foreign matter and method for manufacturing optical detection device Nov 8, 2018 Issued
Array ( [id] => 14079669 [patent_doc_number] => 20190088722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => METHOD FOR MAKING THREE DIMENSIONAL COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CARBON NANOTUBE THIN FILM TRANSISTOR CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/184121 [patent_app_country] => US [patent_app_date] => 2018-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184121 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/184121
Method for making three dimensional complementary metal oxide semiconductor carbon nanotube thin film transistor circuit Nov 7, 2018 Issued
Array ( [id] => 17636162 [patent_doc_number] => 11346882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Enhancement of yield of functional microelectronic devices [patent_app_type] => utility [patent_app_number] => 16/179492 [patent_app_country] => US [patent_app_date] => 2018-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7376 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16179492 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/179492
Enhancement of yield of functional microelectronic devices Nov 1, 2018 Issued
Array ( [id] => 18073911 [patent_doc_number] => 11532754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Array substrate with amorphous silicon shielding layer, manufacturing method thereof, display panel, and display apparatus [patent_app_type] => utility [patent_app_number] => 16/334354 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 8727 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16334354 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/334354
Array substrate with amorphous silicon shielding layer, manufacturing method thereof, display panel, and display apparatus Oct 31, 2018 Issued
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