Search

Robert W. Hodge

Supervisory Patent Examiner (ID: 10805, Phone: (571)272-2097 , Office: P/3655 )

Most Active Art Unit
1795
Art Unit(s)
3655, 1795, 4121, 1746, 1745, 1729, 3649, 3645
Total Applications
436
Issued Applications
181
Pending Applications
28
Abandoned Applications
231

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13559437 [patent_doc_number] => 20180331266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => LED MODULE HAVING LED CHIPS AS LIGHT SOURCE [patent_app_type] => utility [patent_app_number] => 16/033610 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033610 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/033610
LED module having LED chips as light source Jul 11, 2018 Issued
Array ( [id] => 13528699 [patent_doc_number] => 20180315892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => LIGHT EMITTING DEVICE IN WHICH LIGHT EMITTING ELEMENT AND LIGHT TRANSMISSIVE MEMBER ARE DIRECTLY BONDED [patent_app_type] => utility [patent_app_number] => 16/028261 [patent_app_country] => US [patent_app_date] => 2018-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16028261 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/028261
Light emitting device in which light emitting element and light transmissive member are directly bonded Jul 4, 2018 Issued
Array ( [id] => 13832865 [patent_doc_number] => 20190019917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => Epitaxy Technique for Growing Semiconductor Compounds [patent_app_type] => utility [patent_app_number] => 16/021374 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16021374 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/021374
Epitaxy technique for growing semiconductor compounds Jun 27, 2018 Issued
Array ( [id] => 13495521 [patent_doc_number] => 20180299303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => RELATIVE AND ABSOLUTE PRESSURE SENSOR COMBINED ON CHIP [patent_app_type] => utility [patent_app_number] => 16/016867 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16016867 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/016867
RELATIVE AND ABSOLUTE PRESSURE SENSOR COMBINED ON CHIP Jun 24, 2018 Abandoned
Array ( [id] => 13499785 [patent_doc_number] => 20180301435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => SINGLE LAYER LOW COST WAFER LEVEL PACKAGING FOR SFF SIP [patent_app_type] => utility [patent_app_number] => 16/015052 [patent_app_country] => US [patent_app_date] => 2018-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16015052 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/015052
Single layer low cost wafer level packaging for SFF SiP Jun 20, 2018 Issued
Array ( [id] => 16844315 [patent_doc_number] => 11016398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Integrated circuit overlay test patterns and method thereof [patent_app_type] => utility [patent_app_number] => 16/008267 [patent_app_country] => US [patent_app_date] => 2018-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 11163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16008267 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/008267
Integrated circuit overlay test patterns and method thereof Jun 13, 2018 Issued
Array ( [id] => 16502511 [patent_doc_number] => 10867906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-15 [patent_title] => Conductive structures in semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/006120 [patent_app_country] => US [patent_app_date] => 2018-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8272 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16006120 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/006120
Conductive structures in semiconductor devices Jun 11, 2018 Issued
Array ( [id] => 15906013 [patent_doc_number] => 20200152527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => CLEARING OUT METHOD, REVEALING DEVICE, LITHOGRAPHIC APPARATUS, AND DEVICE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 16/625861 [patent_app_country] => US [patent_app_date] => 2018-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16625861 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/625861
CLEARING OUT METHOD, REVEALING DEVICE, LITHOGRAPHIC APPARATUS, AND DEVICE MANUFACTURING METHOD May 27, 2018 Abandoned
Array ( [id] => 15184937 [patent_doc_number] => 20190363060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => APPARATUSES AND METHODS FOR PIN CAPACITANCE REDUCTION INCLUDING BOND PADS AND CIRCUITS IN A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/990370 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3986 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15990370 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/990370
APPARATUSES AND METHODS FOR PIN CAPACITANCE REDUCTION INCLUDING BOND PADS AND CIRCUITS IN A SEMICONDUCTOR DEVICE May 24, 2018 Abandoned
Array ( [id] => 16172816 [patent_doc_number] => 10714393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Middle of the line subtractive self-aligned contacts [patent_app_type] => utility [patent_app_number] => 15/980256 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15980256 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/980256
Middle of the line subtractive self-aligned contacts May 14, 2018 Issued
Array ( [id] => 15488491 [patent_doc_number] => 10559607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Semiconductor device and manufacturing method of semiconductor device [patent_app_type] => utility [patent_app_number] => 15/962567 [patent_app_country] => US [patent_app_date] => 2018-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 7892 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15962567 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/962567
Semiconductor device and manufacturing method of semiconductor device Apr 24, 2018 Issued
Array ( [id] => 16339207 [patent_doc_number] => 10790175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Selective etch rate monitor [patent_app_type] => utility [patent_app_number] => 15/955375 [patent_app_country] => US [patent_app_date] => 2018-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7337 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15955375 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/955375
Selective etch rate monitor Apr 16, 2018 Issued
Array ( [id] => 15641119 [patent_doc_number] => 10593564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Lid attach optimization to limit electronic package warpage [patent_app_type] => utility [patent_app_number] => 15/951439 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 8373 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951439 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/951439
Lid attach optimization to limit electronic package warpage Apr 11, 2018 Issued
Array ( [id] => 15061635 [patent_doc_number] => 10461130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Image device including photoelectric conversion layer [patent_app_type] => utility [patent_app_number] => 15/938374 [patent_app_country] => US [patent_app_date] => 2018-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 12669 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15938374 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/938374
Image device including photoelectric conversion layer Mar 27, 2018 Issued
Array ( [id] => 17978683 [patent_doc_number] => 11495555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Magnetic bilayer structure for a cored or coreless semiconductor package [patent_app_type] => utility [patent_app_number] => 15/921511 [patent_app_country] => US [patent_app_date] => 2018-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 60 [patent_no_of_words] => 19798 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15921511 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/921511
Magnetic bilayer structure for a cored or coreless semiconductor package Mar 13, 2018 Issued
Array ( [id] => 12896953 [patent_doc_number] => 20180190826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/907343 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907343 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907343
Manufacturing method of semiconductor device Feb 27, 2018 Issued
Array ( [id] => 13363637 [patent_doc_number] => 20180233358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => METHOD FOR MANUFACTURING SILICON-CARBIDE SEMICONDUCTOR ELEMENT [patent_app_type] => utility [patent_app_number] => 15/906596 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15906596 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/906596
Method for manufacturing silicon-carbide semiconductor element Feb 26, 2018 Issued
Array ( [id] => 16803265 [patent_doc_number] => 10998217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Thermoplastic temporary adhesive for silicon handler with infra-red laser wafer de-bonding [patent_app_type] => utility [patent_app_number] => 15/900178 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 9452 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900178 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/900178
Thermoplastic temporary adhesive for silicon handler with infra-red laser wafer de-bonding Feb 19, 2018 Issued
Array ( [id] => 16803265 [patent_doc_number] => 10998217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Thermoplastic temporary adhesive for silicon handler with infra-red laser wafer de-bonding [patent_app_type] => utility [patent_app_number] => 15/900178 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 9452 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900178 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/900178
Thermoplastic temporary adhesive for silicon handler with infra-red laser wafer de-bonding Feb 19, 2018 Issued
Array ( [id] => 16987903 [patent_doc_number] => 11075086 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-27 [patent_title] => Method for etching deep, high-aspect ratio features into silicon carbide and gallium nitride [patent_app_type] => utility [patent_app_number] => 15/894067 [patent_app_country] => US [patent_app_date] => 2018-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 40 [patent_no_of_words] => 12703 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 398 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15894067 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/894067
Method for etching deep, high-aspect ratio features into silicon carbide and gallium nitride Feb 11, 2018 Issued
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