
Robert W. Hodge
Supervisory Patent Examiner (ID: 10805, Phone: (571)272-2097 , Office: P/3655 )
| Most Active Art Unit | 1795 |
| Art Unit(s) | 3655, 1795, 4121, 1746, 1745, 1729, 3649, 3645 |
| Total Applications | 436 |
| Issued Applications | 181 |
| Pending Applications | 28 |
| Abandoned Applications | 231 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12162516
[patent_doc_number] => 20180033783
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-01
[patent_title] => 'Avalanche Diode Having an Enhanced Defect Concentration Level and Method of Making the Same'
[patent_app_type] => utility
[patent_app_number] => 15/782582
[patent_app_country] => US
[patent_app_date] => 2017-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6100
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782582
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/782582 | Avalanche diode having an enhanced defect concentration level and method of making the same | Oct 11, 2017 | Issued |
Array
(
[id] => 12693316
[patent_doc_number] => 20180122938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-03
[patent_title] => FABRICATION OF A PAIR OF VERTICAL FIN FIELD EFFECT TRANSISTORS HAVING A MERGED TOP SOURCE/DRAIN
[patent_app_type] => utility
[patent_app_number] => 15/723759
[patent_app_country] => US
[patent_app_date] => 2017-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12162
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15723759
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/723759 | Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain | Oct 2, 2017 | Issued |
Array
(
[id] => 16348145
[patent_doc_number] => 20200312796
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-01
[patent_title] => SUBSTRATE INTEGRATED INDUCTORS USING HIGH THROUGHPUT ADDITIVE DEPOSITION OF HYBRID MAGNETIC MATERIALS
[patent_app_type] => utility
[patent_app_number] => 16/651939
[patent_app_country] => US
[patent_app_date] => 2017-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19782
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16651939
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/651939 | Substrate integrated inductors using high throughput additive deposition of hybrid magnetic materials | Sep 29, 2017 | Issued |
Array
(
[id] => 12150609
[patent_doc_number] => 20180021873
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-25
[patent_title] => 'WELDING SYSTEM WITH POWER LINE COMMUNICATION'
[patent_app_type] => utility
[patent_app_number] => 15/720941
[patent_app_country] => US
[patent_app_date] => 2017-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8901
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720941
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/720941 | WELDING SYSTEM WITH POWER LINE COMMUNICATION | Sep 28, 2017 | Abandoned |
Array
(
[id] => 16081125
[patent_doc_number] => 20200194549
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-18
[patent_title] => MULTI-STEP LATERAL EPITAXIAL OVERGROWTH FOR LOW DEFECT DENSITY III-N FILMS
[patent_app_type] => utility
[patent_app_number] => 16/643446
[patent_app_country] => US
[patent_app_date] => 2017-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19140
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16643446
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/643446 | Multi-step lateral epitaxial overgrowth for low defect density III-N films | Sep 28, 2017 | Issued |
Array
(
[id] => 12154703
[patent_doc_number] => 20180025967
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-25
[patent_title] => 'FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES'
[patent_app_type] => utility
[patent_app_number] => 15/715725
[patent_app_country] => US
[patent_app_date] => 2017-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 12103
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715725
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/715725 | FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES | Sep 25, 2017 | Abandoned |
Array
(
[id] => 16448271
[patent_doc_number] => 10840202
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-17
[patent_title] => Method of forming solder bumps
[patent_app_type] => utility
[patent_app_number] => 15/714146
[patent_app_country] => US
[patent_app_date] => 2017-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 17
[patent_no_of_words] => 3852
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714146
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/714146 | Method of forming solder bumps | Sep 24, 2017 | Issued |
Array
(
[id] => 15598215
[patent_doc_number] => 20200075642
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-05
[patent_title] => METHOD FOR MANUFACTURING ACTIVE ARRAY SWITCH
[patent_app_type] => utility
[patent_app_number] => 15/739312
[patent_app_country] => US
[patent_app_date] => 2017-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3945
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15739312
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/739312 | METHOD FOR MANUFACTURING ACTIVE ARRAY SWITCH | Sep 21, 2017 | Abandoned |
Array
(
[id] => 15475207
[patent_doc_number] => 10553488
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-04
[patent_title] => Device without zero mark layer
[patent_app_type] => utility
[patent_app_number] => 15/710854
[patent_app_country] => US
[patent_app_date] => 2017-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 5774
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15710854
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/710854 | Device without zero mark layer | Sep 20, 2017 | Issued |
Array
(
[id] => 15421315
[patent_doc_number] => 10543564
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-28
[patent_title] => Wafer alignment with restricted visual access
[patent_app_type] => utility
[patent_app_number] => 15/702584
[patent_app_country] => US
[patent_app_date] => 2017-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 9107
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15702584
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/702584 | Wafer alignment with restricted visual access | Sep 11, 2017 | Issued |
Array
(
[id] => 12263894
[patent_doc_number] => 20180083090
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-22
[patent_title] => 'METAL RESISTOR STRUCTURES WITH NITROGEN CONTENT'
[patent_app_type] => utility
[patent_app_number] => 15/690923
[patent_app_country] => US
[patent_app_date] => 2017-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4452
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690923
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/690923 | Metal resistor structures with nitrogen content | Aug 29, 2017 | Issued |
Array
(
[id] => 12122546
[patent_doc_number] => 20180006132
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-04
[patent_title] => 'VARIED SILICON RICHNESS SILICON NITRIDE FORMATION'
[patent_app_type] => utility
[patent_app_number] => 15/690494
[patent_app_country] => US
[patent_app_date] => 2017-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9705
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690494
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/690494 | Varied silicon richness silicon nitride formation | Aug 29, 2017 | Issued |
Array
(
[id] => 16132913
[patent_doc_number] => 10700228
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-30
[patent_title] => Method for manufacturing solar cell module having defect tested solar cell strings
[patent_app_type] => utility
[patent_app_number] => 15/687002
[patent_app_country] => US
[patent_app_date] => 2017-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 27
[patent_no_of_words] => 16098
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687002
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/687002 | Method for manufacturing solar cell module having defect tested solar cell strings | Aug 24, 2017 | Issued |
Array
(
[id] => 15641369
[patent_doc_number] => 10593689
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-17
[patent_title] => Methods for fabricating a semiconductor device and semiconductor devices fabricated by the same
[patent_app_type] => utility
[patent_app_number] => 15/685650
[patent_app_country] => US
[patent_app_date] => 2017-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 61
[patent_no_of_words] => 15267
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15685650
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/685650 | Methods for fabricating a semiconductor device and semiconductor devices fabricated by the same | Aug 23, 2017 | Issued |
Array
(
[id] => 16324445
[patent_doc_number] => 10784421
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-22
[patent_title] => Method of producing an optoelectronic component
[patent_app_type] => utility
[patent_app_number] => 16/326731
[patent_app_country] => US
[patent_app_date] => 2017-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 4504
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16326731
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/326731 | Method of producing an optoelectronic component | Aug 22, 2017 | Issued |
Array
(
[id] => 15673253
[patent_doc_number] => 10600870
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-24
[patent_title] => Semiconductor structure with a silicon germanium alloy fin and silicon germanium alloy pad structure
[patent_app_type] => utility
[patent_app_number] => 15/683310
[patent_app_country] => US
[patent_app_date] => 2017-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 7549
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683310
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/683310 | Semiconductor structure with a silicon germanium alloy fin and silicon germanium alloy pad structure | Aug 21, 2017 | Issued |
Array
(
[id] => 13085001
[patent_doc_number] => 10062573
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-08-28
[patent_title] => Embedded SONOS with triple gate oxide and manufacturing method of the same
[patent_app_type] => utility
[patent_app_number] => 15/683274
[patent_app_country] => US
[patent_app_date] => 2017-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 28
[patent_no_of_words] => 12852
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683274
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/683274 | Embedded SONOS with triple gate oxide and manufacturing method of the same | Aug 21, 2017 | Issued |
Array
(
[id] => 13724209
[patent_doc_number] => 20170373060
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-28
[patent_title] => DEVICE FOR A FINFET
[patent_app_type] => utility
[patent_app_number] => 15/676354
[patent_app_country] => US
[patent_app_date] => 2017-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5252
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15676354
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/676354 | Device for a FinFET | Aug 13, 2017 | Issued |
Array
(
[id] => 14827779
[patent_doc_number] => 10410904
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-10
[patent_title] => Peeling method and peeling apparatus
[patent_app_type] => utility
[patent_app_number] => 15/673018
[patent_app_country] => US
[patent_app_date] => 2017-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 7148
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 363
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15673018
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/673018 | Peeling method and peeling apparatus | Aug 8, 2017 | Issued |
Array
(
[id] => 16433006
[patent_doc_number] => 10833104
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-10
[patent_title] => Array substrate and its fabricating method, display device
[patent_app_type] => utility
[patent_app_number] => 15/745773
[patent_app_country] => US
[patent_app_date] => 2017-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 4585
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 292
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15745773
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/745773 | Array substrate and its fabricating method, display device | Jul 19, 2017 | Issued |