Search

Robert W. Hodge

Supervisory Patent Examiner (ID: 10805, Phone: (571)272-2097 , Office: P/3655 )

Most Active Art Unit
1795
Art Unit(s)
3655, 1795, 4121, 1746, 1745, 1729, 3649, 3645
Total Applications
436
Issued Applications
181
Pending Applications
28
Abandoned Applications
231

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18745587 [patent_doc_number] => 20230354581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => Asymmetric Semiconductor Memory Device Having Electrically Floating Body Transistor [patent_app_type] => utility [patent_app_number] => 18/213396 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33114 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18213396 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/213396
Asymmetric semiconductor memory device having electrically floating body transistor Jun 22, 2023 Issued
Array ( [id] => 18865864 [patent_doc_number] => 20230420301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => SHIELDED MODULE FABRICATION METHODS AND DEVICES [patent_app_type] => utility [patent_app_number] => 18/338293 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11329 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338293 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/338293
SHIELDED MODULE FABRICATION METHODS AND DEVICES Jun 19, 2023 Pending
Array ( [id] => 19873817 [patent_doc_number] => 12266688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Semiconductor device with source/drain contact formed using bottom-up deposition [patent_app_type] => utility [patent_app_number] => 18/331917 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 36 [patent_no_of_words] => 10729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331917 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/331917
Semiconductor device with source/drain contact formed using bottom-up deposition Jun 7, 2023 Issued
Array ( [id] => 19873817 [patent_doc_number] => 12266688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Semiconductor device with source/drain contact formed using bottom-up deposition [patent_app_type] => utility [patent_app_number] => 18/331917 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 36 [patent_no_of_words] => 10729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331917 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/331917
Semiconductor device with source/drain contact formed using bottom-up deposition Jun 7, 2023 Issued
Array ( [id] => 18680063 [patent_doc_number] => 20230317721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => Semiconductor capacitor array layout capable of generating parasitic capacitance toward edge of layout [patent_app_type] => utility [patent_app_number] => 18/204619 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18204619 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/204619
Semiconductor capacitor array layout capable of generating parasitic capacitance toward edge of layout May 31, 2023 Issued
Array ( [id] => 18865960 [patent_doc_number] => 20230420397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/322570 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18322570 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/322570
SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME May 22, 2023 Pending
Array ( [id] => 18735655 [patent_doc_number] => 11804396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers [patent_app_type] => utility [patent_app_number] => 18/200387 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 346 [patent_no_of_words] => 80024 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200387 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/200387
Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers May 21, 2023 Issued
Array ( [id] => 18655220 [patent_doc_number] => 20230301071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => MEMORY AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/321762 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18321762 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/321762
MEMORY AND METHOD FOR MANUFACTURING SAME May 21, 2023 Pending
Array ( [id] => 18655220 [patent_doc_number] => 20230301071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => MEMORY AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/321762 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18321762 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/321762
MEMORY AND METHOD FOR MANUFACTURING SAME May 21, 2023 Pending
Array ( [id] => 18632320 [patent_doc_number] => 20230291230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => HIGHLY FLEXIBLE, ELECTRICAL DISTRIBUTION GRID EDGE ENERGY MANAGER AND ROUTER [patent_app_type] => utility [patent_app_number] => 18/197550 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197550 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/197550
Highly flexible, electrical distribution grid edge energy manager and router May 14, 2023 Issued
Array ( [id] => 19577370 [patent_doc_number] => 20240381662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => FERROELECTRIC MEMORY DEVICE COMPRISING A CHIMNEY SEED STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/316448 [patent_app_country] => US [patent_app_date] => 2023-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18316448 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/316448
FERROELECTRIC MEMORY DEVICE COMPRISING A CHIMNEY SEED STRUCTURE May 11, 2023 Pending
Array ( [id] => 18821030 [patent_doc_number] => 20230395371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 18/315066 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315066 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315066
SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS May 9, 2023 Pending
Array ( [id] => 18821030 [patent_doc_number] => 20230395371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 18/315066 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315066 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315066
SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS May 9, 2023 Pending
Array ( [id] => 18616001 [patent_doc_number] => 20230282740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => HIGH ELECTRON MOBILITY TRANSISTOR AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/195347 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18195347 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/195347
HIGH ELECTRON MOBILITY TRANSISTOR AND FABRICATION METHOD THEREOF May 8, 2023 Pending
Array ( [id] => 18616001 [patent_doc_number] => 20230282740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => HIGH ELECTRON MOBILITY TRANSISTOR AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/195347 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18195347 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/195347
HIGH ELECTRON MOBILITY TRANSISTOR AND FABRICATION METHOD THEREOF May 8, 2023 Pending
Array ( [id] => 20328070 [patent_doc_number] => 12458327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Ultrasonic device, semiconductor device, and method of controlling ultrasonic device [patent_app_type] => utility [patent_app_number] => 18/312332 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4446 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312332 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312332
Ultrasonic device, semiconductor device, and method of controlling ultrasonic device May 3, 2023 Issued
Array ( [id] => 18587661 [patent_doc_number] => 20230269926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => 3D MEMORY CELLS AND ARRAY ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/311167 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311167 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/311167
3D MEMORY CELLS AND ARRAY ARCHITECTURES May 1, 2023 Pending
Array ( [id] => 18587662 [patent_doc_number] => 20230269927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => 3D MEMORY CELLS AND ARRAY ARCHITECTURES AND PROCESSES [patent_app_type] => utility [patent_app_number] => 18/311212 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311212 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/311212
3D MEMORY CELLS AND ARRAY ARCHITECTURES AND PROCESSES May 1, 2023 Pending
Array ( [id] => 19560140 [patent_doc_number] => 20240371932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/310489 [patent_app_country] => US [patent_app_date] => 2023-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18310489 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/310489
INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF Apr 30, 2023 Pending
Array ( [id] => 20217645 [patent_doc_number] => 12414314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Deep trench structure for a capacitive device [patent_app_type] => utility [patent_app_number] => 18/308702 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4432 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308702 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/308702
Deep trench structure for a capacitive device Apr 27, 2023 Issued
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