
Robert W. Hodge
Supervisory Patent Examiner (ID: 10805, Phone: (571)272-2097 , Office: P/3655 )
| Most Active Art Unit | 1795 |
| Art Unit(s) | 3655, 1795, 4121, 1746, 1745, 1729, 3649, 3645 |
| Total Applications | 436 |
| Issued Applications | 181 |
| Pending Applications | 28 |
| Abandoned Applications | 231 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15985235
[patent_doc_number] => 10672957
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[patent_kind] => B2
[patent_issue_date] => 2020-06-02
[patent_title] => LED apparatuses and methods for high lumen output density
[patent_app_type] => utility
[patent_app_number] => 15/654323
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/654323 | LED apparatuses and methods for high lumen output density | Jul 18, 2017 | Issued |
Array
(
[id] => 15760431
[patent_doc_number] => 10622344
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[patent_issue_date] => 2020-04-14
[patent_title] => IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the same
[patent_app_type] => utility
[patent_app_number] => 15/644081
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Array
(
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[patent_title] => FABRICATION OF A PAIR OF VERTICAL FIN FIELD EFFECT TRANSISTORS HAVING A MERGED TOP SOURCE/DRAIN
[patent_app_type] => utility
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Array
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[patent_issue_date] => 2017-09-28
[patent_title] => 'III-V SOLAR CELL STRUCTURE WITH MULTI-LAYER BACK SURFACE FIELD'
[patent_app_type] => utility
[patent_app_number] => 15/619440
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/619440 | III-V solar cell structure with multi-layer back surface field | Jun 9, 2017 | Issued |
Array
(
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[patent_title] => Method of reducing charge loss in non-volatile memories
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Array
(
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[patent_title] => 'Methods for Forming Ceramic Substrates with Via Studs'
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Array
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Array
(
[id] => 15139261
[patent_doc_number] => 10483114
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[patent_issue_date] => 2019-11-19
[patent_title] => Method of manufacturing semiconductor device having a nonvolatile memory and a MISFET
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Array
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Array
(
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[patent_issue_date] => 2020-10-06
[patent_title] => Method of forming solder bumps
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Array
(
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Array
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[patent_title] => Method for removing native oxide and residue from a III-V group containing surface
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Array
(
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Array
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Array
(
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Array
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Array
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