Search

Robert W. Hodge

Supervisory Patent Examiner (ID: 10805, Phone: (571)272-2097 , Office: P/3655 )

Most Active Art Unit
1795
Art Unit(s)
3655, 1795, 4121, 1746, 1745, 1729, 3649, 3645
Total Applications
436
Issued Applications
181
Pending Applications
28
Abandoned Applications
231

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15985235 [patent_doc_number] => 10672957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => LED apparatuses and methods for high lumen output density [patent_app_type] => utility [patent_app_number] => 15/654323 [patent_app_country] => US [patent_app_date] => 2017-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 5966 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15654323 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/654323
LED apparatuses and methods for high lumen output density Jul 18, 2017 Issued
Array ( [id] => 15760431 [patent_doc_number] => 10622344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-14 [patent_title] => IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the same [patent_app_type] => utility [patent_app_number] => 15/644081 [patent_app_country] => US [patent_app_date] => 2017-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3231 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15644081 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/644081
IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the same Jul 6, 2017 Issued
Array ( [id] => 12692620 [patent_doc_number] => 20180122706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => FABRICATION OF A PAIR OF VERTICAL FIN FIELD EFFECT TRANSISTORS HAVING A MERGED TOP SOURCE/DRAIN [patent_app_type] => utility [patent_app_number] => 15/624043 [patent_app_country] => US [patent_app_date] => 2017-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15624043 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/624043
Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain Jun 14, 2017 Issued
Array ( [id] => 11974845 [patent_doc_number] => 20170278999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'III-V SOLAR CELL STRUCTURE WITH MULTI-LAYER BACK SURFACE FIELD' [patent_app_type] => utility [patent_app_number] => 15/619440 [patent_app_country] => US [patent_app_date] => 2017-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6183 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15619440 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/619440
III-V solar cell structure with multi-layer back surface field Jun 9, 2017 Issued
Array ( [id] => 13099133 [patent_doc_number] => 10068912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-04 [patent_title] => Method of reducing charge loss in non-volatile memories [patent_app_type] => utility [patent_app_number] => 15/614271 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 10270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15614271 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/614271
Method of reducing charge loss in non-volatile memories Jun 4, 2017 Issued
Array ( [id] => 12061783 [patent_doc_number] => 20170338127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'Methods for Forming Ceramic Substrates with Via Studs' [patent_app_type] => utility [patent_app_number] => 15/611779 [patent_app_country] => US [patent_app_date] => 2017-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15611779 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/611779
Methods for Forming Ceramic Substrates with Via Studs May 31, 2017 Abandoned
Array ( [id] => 13201725 [patent_doc_number] => 10115783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Semiconductor device, method of manufacturing the same, and signal transmitting/receiving method using the semiconductor device [patent_app_type] => utility [patent_app_number] => 15/598475 [patent_app_country] => US [patent_app_date] => 2017-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3582 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15598475 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/598475
Semiconductor device, method of manufacturing the same, and signal transmitting/receiving method using the semiconductor device May 17, 2017 Issued
Array ( [id] => 15139261 [patent_doc_number] => 10483114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Method of manufacturing semiconductor device having a nonvolatile memory and a MISFET [patent_app_type] => utility [patent_app_number] => 15/592279 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 86 [patent_figures_cnt] => 92 [patent_no_of_words] => 37272 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 379 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592279 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/592279
Method of manufacturing semiconductor device having a nonvolatile memory and a MISFET May 10, 2017 Issued
Array ( [id] => 14920541 [patent_doc_number] => 10431598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Vertical semiconductor device with thinned substrate [patent_app_type] => utility [patent_app_number] => 15/588945 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 15711 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15588945 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/588945
Vertical semiconductor device with thinned substrate May 7, 2017 Issued
Array ( [id] => 16356493 [patent_doc_number] => 10797011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Method of forming solder bumps [patent_app_type] => utility [patent_app_number] => 15/498735 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3851 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15498735 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/498735
Method of forming solder bumps Apr 26, 2017 Issued
Array ( [id] => 18387340 [patent_doc_number] => 11658133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Integrated circuit device [patent_app_type] => utility [patent_app_number] => 16/097384 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3749 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16097384 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/097384
Integrated circuit device Apr 26, 2017 Issued
Array ( [id] => 14955035 [patent_doc_number] => 10438796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Method for removing native oxide and residue from a III-V group containing surface [patent_app_type] => utility [patent_app_number] => 15/496420 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8200 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15496420 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/496420
Method for removing native oxide and residue from a III-V group containing surface Apr 24, 2017 Issued
Array ( [id] => 11997602 [patent_doc_number] => 20170301758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'STACKED BODY AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 15/491690 [patent_app_country] => US [patent_app_date] => 2017-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5600 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15491690 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/491690
Stacked body including graphene film and electronic device including graphene film Apr 18, 2017 Issued
Array ( [id] => 11840366 [patent_doc_number] => 20170222086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'LASER PROCESSING FOR SOLAR CELL BASE AND EMITTER REGIONS' [patent_app_type] => utility [patent_app_number] => 15/491882 [patent_app_country] => US [patent_app_date] => 2017-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3107 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15491882 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/491882
LASER PROCESSING FOR SOLAR CELL BASE AND EMITTER REGIONS Apr 18, 2017 Abandoned
Array ( [id] => 11983560 [patent_doc_number] => 20170287715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'ALUMINUM OXIDE PASSIVATION FOR SOLAR CELLS' [patent_app_type] => utility [patent_app_number] => 15/491906 [patent_app_country] => US [patent_app_date] => 2017-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8781 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15491906 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/491906
ALUMINUM OXIDE PASSIVATION FOR SOLAR CELLS Apr 18, 2017 Abandoned
Array ( [id] => 12693310 [patent_doc_number] => 20180122936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => FABRICATION OF A PAIR OF VERTICAL FIN FIELD EFFECT TRANSISTORS HAVING A MERGED TOP SOURCE/DRAIN [patent_app_type] => utility [patent_app_number] => 15/488089 [patent_app_country] => US [patent_app_date] => 2017-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15488089 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/488089
Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain Apr 13, 2017 Issued
Array ( [id] => 15170355 [patent_doc_number] => 10490684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Method for producing a compound photovoltaic cell [patent_app_type] => utility [patent_app_number] => 15/483633 [patent_app_country] => US [patent_app_date] => 2017-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 7836 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15483633 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/483633
Method for producing a compound photovoltaic cell Apr 9, 2017 Issued
Array ( [id] => 13485449 [patent_doc_number] => 20180294267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => SELF ALIGNED BURIED POWER RAIL [patent_app_type] => utility [patent_app_number] => 15/481826 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15481826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/481826
Self aligned buried power rail Apr 6, 2017 Issued
Array ( [id] => 15488131 [patent_doc_number] => 10559422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Electronic device and method for fabricating the same using treatment with nitrogen and hydrogen [patent_app_type] => utility [patent_app_number] => 15/482548 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 13829 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15482548 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/482548
Electronic device and method for fabricating the same using treatment with nitrogen and hydrogen Apr 6, 2017 Issued
Array ( [id] => 14985547 [patent_doc_number] => 10446695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Planar multi-implanted JFET [patent_app_type] => utility [patent_app_number] => 15/482139 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 6593 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15482139 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/482139
Planar multi-implanted JFET Apr 6, 2017 Issued
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