Search

Robert W. Hodge

Supervisory Patent Examiner (ID: 10805, Phone: (571)272-2097 , Office: P/3655 )

Most Active Art Unit
1795
Art Unit(s)
3655, 1795, 4121, 1746, 1745, 1729, 3649, 3645
Total Applications
436
Issued Applications
181
Pending Applications
28
Abandoned Applications
231

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18040213 [patent_doc_number] => 20220384430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => ELECTRODE STRUCTURE, SEMICONDUCTOR STRUCTURE, AND MANUFACTURING METHOD OF ELECTRODE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/886230 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17886230 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/886230
ELECTRODE STRUCTURE, SEMICONDUCTOR STRUCTURE, AND MANUFACTURING METHOD OF ELECTRODE STRUCTURE Aug 10, 2022 Pending
Array ( [id] => 18040213 [patent_doc_number] => 20220384430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => ELECTRODE STRUCTURE, SEMICONDUCTOR STRUCTURE, AND MANUFACTURING METHOD OF ELECTRODE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/886230 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17886230 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/886230
ELECTRODE STRUCTURE, SEMICONDUCTOR STRUCTURE, AND MANUFACTURING METHOD OF ELECTRODE STRUCTURE Aug 10, 2022 Pending
Array ( [id] => 18617796 [patent_doc_number] => 20230284537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/884790 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884790 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884790
MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY DEVICE Aug 9, 2022 Pending
Array ( [id] => 18959024 [patent_doc_number] => 20240047351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => MULTISTEP ETCH FOR DIRECT CHIP ATTACH (DCA) SUBSTRATES, AND ASSOCIATED SYSTEMS AND DEVICES [patent_app_type] => utility [patent_app_number] => 17/882441 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17882441 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/882441
MULTISTEP ETCH FOR DIRECT CHIP ATTACH (DCA) SUBSTRATES, AND ASSOCIATED SYSTEMS AND DEVICES Aug 4, 2022 Pending
Array ( [id] => 18272482 [patent_doc_number] => 20230093724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR WAFERS [patent_app_type] => utility [patent_app_number] => 17/876067 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876067
MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR WAFERS Jul 27, 2022 Abandoned
Array ( [id] => 18008761 [patent_doc_number] => 20220367528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/876063 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876063 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876063
Thin film transistor semiconductor device Jul 27, 2022 Issued
Array ( [id] => 17993668 [patent_doc_number] => 20220359705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING GATE OR CONTACT PLUGS [patent_app_type] => utility [patent_app_number] => 17/871693 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871693 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/871693
Self-aligned gate endcap (SAGE) architecture having gate or contact plugs Jul 21, 2022 Issued
Array ( [id] => 18008699 [patent_doc_number] => 20220367466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Semiconductor Devices with System on Chip Devices [patent_app_type] => utility [patent_app_number] => 17/870296 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870296 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/870296
Method of manufacturing semiconductor devices with system on chip devices Jul 20, 2022 Issued
Array ( [id] => 19679481 [patent_doc_number] => 12191354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Vertical transistors having at least 50% grain boundaries offset between top and bottom source/drain regions and the channel region that is vertically therebetween [patent_app_type] => utility [patent_app_number] => 17/860325 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 8842 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860325
Vertical transistors having at least 50% grain boundaries offset between top and bottom source/drain regions and the channel region that is vertically therebetween Jul 7, 2022 Issued
Array ( [id] => 18156126 [patent_doc_number] => 11569117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => 3D semiconductor device and structure with single-crystal layers [patent_app_type] => utility [patent_app_number] => 17/855775 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 346 [patent_no_of_words] => 79590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855775 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/855775
3D semiconductor device and structure with single-crystal layers Jun 29, 2022 Issued
Array ( [id] => 19335654 [patent_doc_number] => 20240250084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => METHOD FOR OPTIMIZING PROTECTION CIRCUITS OF ELECTRONIC DEVICE CHIPS IN A WAFER [patent_app_type] => utility [patent_app_number] => 17/923595 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17923595 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/923595
METHOD FOR OPTIMIZING PROTECTION CIRCUITS OF ELECTRONIC DEVICE CHIPS IN A WAFER Jun 27, 2022 Abandoned
Array ( [id] => 19335654 [patent_doc_number] => 20240250084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => METHOD FOR OPTIMIZING PROTECTION CIRCUITS OF ELECTRONIC DEVICE CHIPS IN A WAFER [patent_app_type] => utility [patent_app_number] => 17/923595 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17923595 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/923595
METHOD FOR OPTIMIZING PROTECTION CIRCUITS OF ELECTRONIC DEVICE CHIPS IN A WAFER Jun 27, 2022 Abandoned
Array ( [id] => 19335654 [patent_doc_number] => 20240250084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => METHOD FOR OPTIMIZING PROTECTION CIRCUITS OF ELECTRONIC DEVICE CHIPS IN A WAFER [patent_app_type] => utility [patent_app_number] => 17/923595 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17923595 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/923595
METHOD FOR OPTIMIZING PROTECTION CIRCUITS OF ELECTRONIC DEVICE CHIPS IN A WAFER Jun 27, 2022 Abandoned
Array ( [id] => 18263093 [patent_doc_number] => 11610802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes [patent_app_type] => utility [patent_app_number] => 17/846012 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 345 [patent_no_of_words] => 79872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846012 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/846012
Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes Jun 21, 2022 Issued
Array ( [id] => 17900919 [patent_doc_number] => 20220310581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/839431 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17839431 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/839431
Memory device having multiple chips and method for manufacturing the same Jun 12, 2022 Issued
Array ( [id] => 18286873 [patent_doc_number] => 20230102345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => PLANAR SURFACES ON SUBSTRATES [patent_app_type] => utility [patent_app_number] => 17/834837 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834837 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/834837
Device with dummy metallic traces Jun 6, 2022 Issued
Array ( [id] => 18743569 [patent_doc_number] => 20230352557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/833885 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833885 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/833885
Semiconductor device including III-V compound semiconductor layer and manufacturing method thereof Jun 5, 2022 Issued
Array ( [id] => 19926387 [patent_doc_number] => 12300683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Display device with stacked wiring and display device with translucent region [patent_app_type] => utility [patent_app_number] => 17/830470 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8107 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17830470 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/830470
Display device with stacked wiring and display device with translucent region Jun 1, 2022 Issued
Array ( [id] => 17870733 [patent_doc_number] => 20220293470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => INTEGRATED CIRCUIT IN HYBRID ROW HEIGHT STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/831110 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831110 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831110
Integrated circuit in hybrid row height structure Jun 1, 2022 Issued
Array ( [id] => 19957361 [patent_doc_number] => 12327780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Semiconductor device including a lead and a sealing resin [patent_app_type] => utility [patent_app_number] => 17/831143 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3440 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831143 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831143
Semiconductor device including a lead and a sealing resin Jun 1, 2022 Issued
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