Search

Robert Wayne Horn

Examiner (ID: 7557, Phone: (571)272-8591 , Office: P/2837 )

Most Active Art Unit
2837
Art Unit(s)
2832, 2837
Total Applications
1919
Issued Applications
1653
Pending Applications
29
Abandoned Applications
267

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19919838 [patent_doc_number] => 12295234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Display substrate and manufacturing method therefor, and display panel and display device [patent_app_type] => utility [patent_app_number] => 17/776817 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 37 [patent_no_of_words] => 4732 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17776817 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/776817
Display substrate and manufacturing method therefor, and display panel and display device Jan 4, 2021 Issued
Array ( [id] => 18947426 [patent_doc_number] => 11890702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Solder joint [patent_app_type] => utility [patent_app_number] => 17/134881 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 13416 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134881 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134881
Solder joint Dec 27, 2020 Issued
Array ( [id] => 19918607 [patent_doc_number] => 12293983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Conductive pillar, method for manufacturing the same, and method for manufacturing bonded structure [patent_app_type] => utility [patent_app_number] => 17/791652 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 19428 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17791652 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/791652
Conductive pillar, method for manufacturing the same, and method for manufacturing bonded structure Dec 16, 2020 Issued
Array ( [id] => 17941753 [patent_doc_number] => 11476212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Semiconductor contact structure having stress buffer layer formed between under bump metal layer and copper pillar [patent_app_type] => utility [patent_app_number] => 17/123132 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 34 [patent_no_of_words] => 6790 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123132 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123132
Semiconductor contact structure having stress buffer layer formed between under bump metal layer and copper pillar Dec 15, 2020 Issued
Array ( [id] => 17893285 [patent_doc_number] => 11456267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Fet construction with copper pillars or bump directly over the fet [patent_app_type] => utility [patent_app_number] => 17/124485 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4424 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124485 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124485
Fet construction with copper pillars or bump directly over the fet Dec 15, 2020 Issued
Array ( [id] => 17660821 [patent_doc_number] => 20220181286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => TRANSFERRABLE PILLAR STRUCTURE FOR FANOUT PACKAGE OR INTERCONNECT BRIDGE [patent_app_type] => utility [patent_app_number] => 17/115882 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115882
Transferrable pillar structure for fanout package or interconnect bridge Dec 8, 2020 Issued
Array ( [id] => 18156198 [patent_doc_number] => 11569190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/115548 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 4400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115548 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115548
Semiconductor structure and manufacturing method thereof Dec 7, 2020 Issued
Array ( [id] => 18767030 [patent_doc_number] => 11817442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Hybrid manufacturing for integrated circuit devices and assemblies [patent_app_type] => utility [patent_app_number] => 17/114700 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 61 [patent_no_of_words] => 46878 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114700 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114700
Hybrid manufacturing for integrated circuit devices and assemblies Dec 7, 2020 Issued
Array ( [id] => 17825798 [patent_doc_number] => 11430752 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-30 [patent_title] => Low cost millimiter wave integrated LTCC package [patent_app_type] => utility [patent_app_number] => 17/112604 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 7699 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112604 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/112604
Low cost millimiter wave integrated LTCC package Dec 3, 2020 Issued
Array ( [id] => 17908803 [patent_doc_number] => 11462668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Stacked semiconductor device, and set of onboard-components, body and jointing-elements to be used in the stacked semiconductor device [patent_app_type] => utility [patent_app_number] => 17/107844 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 32459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107844 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107844
Stacked semiconductor device, and set of onboard-components, body and jointing-elements to be used in the stacked semiconductor device Nov 29, 2020 Issued
Array ( [id] => 17645332 [patent_doc_number] => 20220173071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => INTERFACIAL TILT-RESISTANT BONDED ASSEMBLY AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/106884 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106884 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106884
Interfacial tilt-resistant bonded assembly and methods for forming the same Nov 29, 2020 Issued
Array ( [id] => 16936530 [patent_doc_number] => 20210202419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => WLCSP PACKAGE WITH DIFFERENT SOLDER VOLUMES [patent_app_type] => utility [patent_app_number] => 17/104968 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104968 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104968
WLCSP package with different solder volumes Nov 24, 2020 Issued
Array ( [id] => 16858454 [patent_doc_number] => 20210159199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/950789 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950789 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/950789
Semiconductor device Nov 16, 2020 Issued
Array ( [id] => 17716638 [patent_doc_number] => 11380637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Efficient redistribution layer topology [patent_app_type] => utility [patent_app_number] => 16/950708 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 5121 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950708 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/950708
Efficient redistribution layer topology Nov 16, 2020 Issued
Array ( [id] => 16677464 [patent_doc_number] => 20210066230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => CHIP PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/097572 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097572 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097572
Chip package structure Nov 12, 2020 Issued
Array ( [id] => 18057011 [patent_doc_number] => 20220388097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => Method for creating shunt free translucent flexible thin-film photovoltaic module [patent_app_type] => utility [patent_app_number] => 17/774864 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17774864 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/774864
Method for creating shunt free translucent flexible thin-film photovoltaic module Nov 11, 2020 Issued
Array ( [id] => 17583003 [patent_doc_number] => 20220139858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => PILLAR BUMP WITH NOBLE METAL SEED LAYER FOR ADVANCED HETEROGENEOUS INTEGRATION [patent_app_type] => utility [patent_app_number] => 17/089199 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089199 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/089199
Pillar bump with noble metal seed layer for advanced heterogeneous integration Nov 3, 2020 Issued
Array ( [id] => 19330448 [patent_doc_number] => 12048148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Three-dimensional memory devices and methods for forming the same [patent_app_type] => utility [patent_app_number] => 17/084401 [patent_app_country] => US [patent_app_date] => 2020-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 11417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084401 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/084401
Three-dimensional memory devices and methods for forming the same Oct 28, 2020 Issued
Array ( [id] => 17993815 [patent_doc_number] => 20220359852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => MASK ASSEMBLY, DISPLAY PANEL, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/631118 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17631118 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/631118
Mask assembly, display panel, and display device Oct 19, 2020 Issued
Array ( [id] => 17551598 [patent_doc_number] => 20220122940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SEMICONDUCTOR DEVICE ASSEMBLY WITH PRE-REFLOWED SOLDER [patent_app_type] => utility [patent_app_number] => 17/074182 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/074182
Semiconductor device assembly with pre-reflowed solder Oct 18, 2020 Issued
Menu