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Robert Whittenbaugh

Examiner (ID: 10240)

Most Active Art Unit
1201
Art Unit(s)
1201
Total Applications
889
Issued Applications
802
Pending Applications
0
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19204717 [patent_doc_number] => 20240176616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => PROCESSOR AND METHOD OF CONTROLLING PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/519635 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519635 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/519635
Processor and method of controlling processor Nov 26, 2023 Issued
Array ( [id] => 19764603 [patent_doc_number] => 12222893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Connectivity in coarse grained reconfigurable architecture [patent_app_type] => utility [patent_app_number] => 18/388784 [patent_app_country] => US [patent_app_date] => 2023-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 23959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18388784 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/388784
Connectivity in coarse grained reconfigurable architecture Nov 9, 2023 Issued
Array ( [id] => 19069433 [patent_doc_number] => 20240103859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => SYSTEM AND METHOD FOR DIVIDE-AND-CONQUER CHECKPOINTING [patent_app_type] => utility [patent_app_number] => 18/494357 [patent_app_country] => US [patent_app_date] => 2023-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18494357 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/494357
System and method for divide-and-conquer checkpointing Oct 24, 2023 Issued
Array ( [id] => 19992582 [patent_doc_number] => 20250130804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => TECHNIQUES FOR OPTIMIZING STORE OF COMMON VALUES TO MEMORY STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/490690 [patent_app_country] => US [patent_app_date] => 2023-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18490690 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/490690
TECHNIQUES FOR OPTIMIZING STORE OF COMMON VALUES TO MEMORY STRUCTURES Oct 18, 2023 Pending
Array ( [id] => 19985752 [patent_doc_number] => 20250123974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => DETERMINATION OF ACTIVE AND STANDBY SMART NICS THROUGH DATAPATH [patent_app_type] => utility [patent_app_number] => 18/380859 [patent_app_country] => US [patent_app_date] => 2023-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18380859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/380859
DETERMINATION OF ACTIVE AND STANDBY SMART NICS THROUGH DATAPATH Oct 16, 2023 Abandoned
Array ( [id] => 19925164 [patent_doc_number] => 12299449 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-13 [patent_title] => Performance and power efficient processor when switching between fetching from decoded and non-decoded instruction sources [patent_app_type] => utility [patent_app_number] => 18/380150 [patent_app_country] => US [patent_app_date] => 2023-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 35597 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18380150 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/380150
Performance and power efficient processor when switching between fetching from decoded and non-decoded instruction sources Oct 12, 2023 Issued
Array ( [id] => 19174472 [patent_doc_number] => 20240160446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => Predicting a Vector Length Associated with a Configuration Instruction [patent_app_type] => utility [patent_app_number] => 18/484128 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18484128 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/484128
Predicting a Vector Length Associated with a Configuration Instruction Oct 9, 2023 Pending
Array ( [id] => 18925775 [patent_doc_number] => 20240028779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => HARDWARE-BASED SECURITY AUTHENTICATION [patent_app_type] => utility [patent_app_number] => 18/376928 [patent_app_country] => US [patent_app_date] => 2023-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18376928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/376928
Hardware-based security authentication Oct 4, 2023 Issued
Array ( [id] => 19905770 [patent_doc_number] => 12282778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Selective use of branch prediction hints [patent_app_type] => utility [patent_app_number] => 18/479974 [patent_app_country] => US [patent_app_date] => 2023-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18479974 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/479974
Selective use of branch prediction hints Oct 2, 2023 Issued
Array ( [id] => 19780042 [patent_doc_number] => 12229075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Transaction layer packet format [patent_app_type] => utility [patent_app_number] => 18/478595 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 23494 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18478595 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/478595
Transaction layer packet format Sep 28, 2023 Issued
Array ( [id] => 18904636 [patent_doc_number] => 20240020121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => VECTOR FLOATING-POINT CLASSIFICATION [patent_app_type] => utility [patent_app_number] => 18/476604 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18476604 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/476604
Vector floating-point classification Sep 27, 2023 Issued
Array ( [id] => 19864549 [patent_doc_number] => 20250103335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => PROCESSING UNIT INCLUDING A DYNAMICALLY ALLOCATABLE VECTOR REGISTER FILE FOR NON-VECTOR INSTRUCTION PROCESSING [patent_app_type] => utility [patent_app_number] => 18/475320 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8087 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475320 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475320
Processing unit including a dynamically allocatable vector register file for non-vector instruction processing Sep 26, 2023 Issued
Array ( [id] => 19669814 [patent_doc_number] => 12182573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Processing device with vector transformation execution [patent_app_type] => utility [patent_app_number] => 18/370487 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18370487 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/370487
Processing device with vector transformation execution Sep 19, 2023 Issued
Array ( [id] => 19803560 [patent_doc_number] => 20250069485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => DEPLOYING IMMUTABLE IMAGE SOFTWARE VIA MEMORY PARTITION OF BRANCH RETAIL DEVICES [patent_app_type] => utility [patent_app_number] => 18/370806 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18370806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/370806
Deploying immutable image software via memory partition of branch retail devices Sep 19, 2023 Issued
Array ( [id] => 19267598 [patent_doc_number] => 20240211301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => COMPUTER-READABLE RECORDING MEDIUM STORING DATA CONTROL PROGRAM, DATA CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 18/463375 [patent_app_country] => US [patent_app_date] => 2023-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18463375 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/463375
COMPUTER-READABLE RECORDING MEDIUM STORING DATA CONTROL PROGRAM, DATA CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS Sep 7, 2023 Abandoned
Array ( [id] => 19756542 [patent_doc_number] => 20250045107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => SPARSE MATRIX MULTIPLICATION IN A NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 18/240281 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 88546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18240281 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/240281
Sparse matrix multiplication in a neural network Aug 29, 2023 Issued
Array ( [id] => 20595252 [patent_doc_number] => 12578968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Systems and methods for branch pre-resolution by software-provided hardware-managed backslice execution [patent_app_type] => utility [patent_app_number] => 18/239490 [patent_app_country] => US [patent_app_date] => 2023-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 7151 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18239490 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/239490
Systems and methods for branch pre-resolution by software-provided hardware-managed backslice execution Aug 28, 2023 Issued
Array ( [id] => 19347314 [patent_doc_number] => 20240256277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => NEAR-MEMORY OPERATOR AND METHOD WITH ACCELERATOR PERFORMANCE IMPROVEMENT [patent_app_type] => utility [patent_app_number] => 18/456874 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10301 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18456874 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/456874
Near-memory operator and method with accelerator performance improvement Aug 27, 2023 Issued
Array ( [id] => 18847085 [patent_doc_number] => 20230409489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => Apparatus and Method for Selecting Dynamic Latency for Level 2 Cache [patent_app_type] => utility [patent_app_number] => 18/238098 [patent_app_country] => US [patent_app_date] => 2023-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18238098 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/238098
Apparatus and method for selecting dynamic latency for level 2 cache Aug 24, 2023 Issued
Array ( [id] => 20130905 [patent_doc_number] => 12373218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Technique for predicting behaviour of control flow instructions [patent_app_type] => utility [patent_app_number] => 18/454158 [patent_app_country] => US [patent_app_date] => 2023-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 21326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18454158 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/454158
Technique for predicting behaviour of control flow instructions Aug 22, 2023 Issued
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